Digital Implementation

Latest Posts

Discussion

Encounter Test run-time error

Category: Digital Implementation

By jamesASIC

$usertype
•
updated over 14 years ago by dft1

1 replies • 13583 views
Discussion

Exclude macros from addMetalFill

Category: Digital Implementation

By Johann Glaser

$usertype
•
updated over 14 years ago by Johann Glaser

2 replies • 13858 views
Discussion

db command to get power pin co-ordinates for a given Macro

Category: Digital Implementation

By deeps

$usertype
•
updated over 14 years ago by PradyK

11 replies • 22085 views
Discussion

pin location

Category: Digital Implementation

By Yemelya

$usertype
•
updated over 14 years ago by PradyK

8 replies • 15544 views
Discussion

Multi cut Issue

Category: Digital Implementation

By Shivareddy

$usertype
•
updated over 14 years ago by Scrivner

1 replies • 13401 views
Discussion

post-sim failed

Category: Digital Implementation

By cashen

$usertype
•
updated over 14 years ago by Scrivner

1 replies • 14914 views
Discussion

how to validate delay change details reported due to cross talk effect in spice

Category: Digital Implementation

By deeps

$usertype
•
started over 14 years ago

0 replies • 13230 views
Discussion

State Dependent Problem in db_output and alf2lib

Category: Digital Implementation

By Chiahsiang

$usertype
•
started over 14 years ago

0 replies • 13197 views
Discussion

Convert Wire to be a Pin

Category: Digital Implementation

By Yemelya

$usertype
•
started over 14 years ago

0 replies • 13183 views
Discussion

create_generated_clock works?

Category: Digital Implementation

By mwhite

$usertype
•
updated over 14 years ago by wally1

1 replies • 15523 views
Discussion

ELC Simulation { ... dc ??? } Documentation

Category: Digital Implementation

By Natan00

$usertype
•
started over 14 years ago

0 replies • 13286 views
Discussion

Compatibility problem between ELC and Verilog-A

Category: Digital Implementation

By Bastien

$usertype
•
updated over 14 years ago by rangha

1 replies • 13722 views
Discussion

Number of clock gated components

Category: Digital Implementation

By Shivareddy

$usertype
•
updated over 14 years ago by wally1

3 replies • 14171 views
Discussion

a doubt while designing a cmos inverter in cadence 614

Category: Digital Implementation

By suman samui

$usertype
•
started over 14 years ago

0 replies • 13178 views
Discussion

Timing Engine isues **ERROR: (TA-152) complaining about generated clock edges (was: an Error during placement?)

Category: Digital Implementation

By icmaple

$usertype
•
updated over 14 years ago by Shivareddy

5 replies • 20268 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.