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Functional Verification

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    Reg : problem with reg declaration in IUS58

    Category: Functional Verification

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    updated over 18 years ago by archive

    4 replies • 14979 views
  • Discussion

    printf in IUS6.01

    Category: Functional Verification

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    updated over 18 years ago by archive

    6 replies • 16276 views
  • Discussion

    forall and endpoint/ended

    Category: Functional Verification

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    updated over 18 years ago by archive

    1 replies • 1173 views
  • Discussion

    Please update IPCM website

    Category: Functional Verification

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    updated over 18 years ago by archive

    2 replies • 14095 views
  • Discussion

    BFM written in class has to interface with phy signals

    Category: Functional Verification

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    updated over 18 years ago by archive

    16 replies • 24472 views
  • Discussion

    file I/O

    Category: Functional Verification

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    updated over 18 years ago by archive

    1 replies • 1058 views
  • Discussion

    generic task for hdl node force/release in system verilog

    Category: Functional Verification

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    updated over 18 years ago by archive

    1 replies • 2945 views
  • Discussion

    waveform dump problem using SystemVerilog

    Category: Functional Verification

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    updated over 18 years ago by archive

    6 replies • 19943 views
  • Discussion

    c routines used in specman

    Category: Functional Verification

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    updated over 18 years ago by archive

    1 replies • 13792 views
  • Discussion

    Wand Wires to be driven by Program Block and Module block

    Category: Functional Verification

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    updated over 18 years ago by archive

    10 replies • 18754 views
  • Discussion

    CDNLive! 2007: What will YOU be looking out for?

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 14383 views
  • Discussion

    Replication Patterns

    Category: Functional Verification

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    updated over 18 years ago by archive

    6 replies • 16331 views
  • Discussion

    problem:: Functional coverage analysis

    Category: Functional Verification

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    updated over 18 years ago by archive

    1 replies • 13822 views
  • Discussion

    vhdl & system verilog

    Category: Functional Verification

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    updated over 18 years ago by archive

    10 replies • 10523 views
  • Discussion

    dynamic probes

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 14745 views
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