Functional Verification

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UNDERSTANDING CADENCE JTAG VIP DEMO

Category: Functional Verification

By navarora

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started over 13 years ago

0 replies • 13834 views
Discussion

irun: design.v is verilog and verilog AMS

Category: Functional Verification

By moogyd

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updated over 13 years ago by moogyd

2 replies • 16404 views
Discussion

Viewing dynamic objects in the Simvision waveform window

Category: Functional Verification

By SCollins

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started over 13 years ago

0 replies • 15645 views
Discussion

Switch to run through assertions

Category: Functional Verification

By Teeeravis

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updated over 13 years ago by tpylant

3 replies • 19328 views
Discussion

How to match the UVC version & the cdn_e_utils version

Category: Functional Verification

By giridhara

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started over 13 years ago

0 replies • 650 views
Discussion

time between two events

Category: Functional Verification

By pravintavagad

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updated over 13 years ago by StephenH

4 replies • 15748 views
Discussion

list generation

Category: Functional Verification

By guyl

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updated over 13 years ago by hannes

1 replies • 13844 views
Discussion

print all the `defines

Category: Functional Verification

By dechaoz05

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updated over 13 years ago by hannes

1 replies • 14698 views
Discussion

How to filter X -> 0 or X -> 1 from signals for events

Category: Functional Verification

By jaichandra

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updated over 13 years ago by hannes

3 replies • 1601 views
Discussion

XBus XSoC XSerial examples

Category: Functional Verification

By pravintavagad

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updated over 13 years ago by hannes

1 replies • 13831 views
Discussion

passing events as parameters to methods or TCM

Category: Functional Verification

By jaichandra

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updated over 13 years ago by hannes

1 replies • 13668 views
Discussion

SystemVerilog modport question

Category: Functional Verification

By SCollins

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updated over 13 years ago by SCollins

2 replies • 18229 views
Discussion

Use of a specify block within a SystemVerilog interface

Category: Functional Verification

By SCollins

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updated over 13 years ago by SCollins

1 replies • 18285 views
Discussion

irun 11.10-s062 -R option and *W,WKWTLK "Waiting for a Exclusive lock"

Category: Functional Verification

By cubicle82

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started over 13 years ago

0 replies • 3245 views
Discussion

Generation of EVCD file for Verilog-AMS

Category: Functional Verification

By Anky

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started over 13 years ago

0 replies • 15458 views

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