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Functional Verification

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  • Discussion

    Concatenating enumerated types in coverpoint

    Category: Functional Verification

    By RajeshCM RajeshCM

    •

    updated over 13 years ago by tpylant

    4 replies • 15852 views
  • Discussion

    Looking for help with System Verilog in AMS

    Category: Functional Verification

    By JRAHildebrand JRAHildebrand

    •

    updated over 13 years ago by Shalom B

    12 replies • 18941 views
  • Discussion

    Need help when using the AMS-Ultrasim tools,occuring some problems in Electrical signal to Logical signal connect module

    Category: Functional Verification

    By zhangyz zhangyz

    •

    started over 13 years ago

    0 replies • 400 views
  • Discussion

    tk plugin error in ncsim

    Category: Functional Verification

    By NormanW NormanW

    •

    updated over 13 years ago by StephenH

    1 replies • 13543 views
  • Discussion

    How to apply Dynamic Load and Reseed Methodology into UVM

    Category: Functional Verification

    By clacasse clacasse

    •

    started over 13 years ago

    0 replies • 12927 views
  • Discussion

    Re: How to Simulate 64-bit VHDL Code in Cadence?

    Category: Functional Verification

    By grasshopper grasshopper

    •

    started over 13 years ago

    0 replies • 12669 views
  • Discussion

    How to save the signals in waveform window?

    Category: Functional Verification

    By rohslogic rohslogic

    •

    updated over 13 years ago by TAM1

    1 replies • 26980 views
  • Discussion

    Internal error during elabration phase

    Category: Functional Verification

    By mdkaleem mdkaleem

    •

    updated over 13 years ago by mdkaleem

    6 replies • 15408 views
  • Discussion

    IMC Coverage

    Category: Functional Verification

    By MDK1234 MDK1234

    •

    updated over 13 years ago by StephenH

    3 replies • 21603 views
  • Discussion

    Forcing a VHDL signal from a Verilog Test/Env

    Category: Functional Verification

    By ashfaqh ashfaqh

    •

    updated over 13 years ago by ravisguptaji

    4 replies • 7184 views
  • Discussion

    cannot use $cds_analog_exists() or $cgav()

    Category: Functional Verification

    By freitas freitas

    •

    updated over 13 years ago by freitas

    1 replies • 14024 views
  • Discussion

    ncverilog simulation verilog: error fmuk

    Category: Functional Verification

    By weebey weebey

    •

    updated over 13 years ago by weebey

    5 replies • 25721 views
  • Discussion

    simvision plugins - tcl tk 8.5? tcl 8.4 tile? c++ qt?

    Category: Functional Verification

    By tomers tomers

    •

    updated over 13 years ago by Doug Koslow

    3 replies • 2000 views
  • Discussion

    "INTERNAL EXCEPTION" when ncsim

    Category: Functional Verification

    By Tommy zou Tommy zou

    •

    started over 13 years ago

    0 replies • 3146 views
  • Discussion

    Using interface signals as coverpoint bins

    Category: Functional Verification

    By RajeshCM RajeshCM

    •

    updated over 13 years ago by TAM1

    1 replies • 15913 views
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