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Functional Verification

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  • Discussion

    Including `defines with ncvlog netlisting

    Category: Functional Verification

    By casparvv casparvv

    •

    updated over 8 years ago by casparvv

    2 replies • 15948 views
  • Discussion

    Blank screen emanager

    Category: Functional Verification

    By Paludo Paludo

    •

    updated over 8 years ago by snitkau

    1 replies • 13135 views
  • Discussion

    Exclude a net from block coverage

    Category: Functional Verification

    By Sandeep4386 Sandeep4386

    •

    updated over 8 years ago by StephenH

    3 replies • 16354 views
  • Discussion

    Verilog instantiating SystemC (generated using Verilator). irun error: Could not load SystemC model library.

    Category: Functional Verification

    By ninadpachpute ninadpachpute

    •

    updated over 8 years ago by StephenH

    1 replies • 14459 views
  • Discussion

    [IUS] Code profiling

    Category: Functional Verification

    By stanzani stanzani

    •

    updated over 8 years ago by StephenH

    1 replies • 13554 views
  • Discussion

    JasperGold connectivity check.

    Category: Functional Verification

    By sruti sruti

    •

    started over 8 years ago

    0 replies • 14258 views
  • Discussion

    JasperGold connectivity check

    Category: Functional Verification

    By sruti sruti

    •

    started over 8 years ago

    0 replies • 14131 views
  • Discussion

    Problem with user define net types resolution functions

    Category: Functional Verification

    By jach78 jach78

    •

    updated over 8 years ago by tpylant

    6 replies • 17513 views
  • Discussion

    I am checking the code coverage for one of my Module's testbench, but the expression coverage is appearing as "n/a" , why is that so ? there are if-else & assignments in the RTL... how do I enable it ?

    Category: Functional Verification

    By Saru K S Saru K S

    •

    updated over 8 years ago by StephenH

    4 replies • 3509 views
  • Discussion

    Quickly schematic-viewing a gates file

    Category: Functional Verification

    By Almendrico Almendrico

    •

    updated over 8 years ago by Doug Koslow

    5 replies • 16974 views
  • Discussion

    [AHB eVC]Unexpected 1ps delay on BFM

    Category: Functional Verification

    By J1EM1N J1EM1N

    •

    started over 8 years ago

    0 replies • 380 views
  • Discussion

    How to generate illegal AHB transactions using eVC

    Category: Functional Verification

    By J1EM1N J1EM1N

    •

    started over 8 years ago

    0 replies • 12683 views
  • Discussion

    Black Blox Creation

    Category: Functional Verification

    By jesolano jesolano

    •

    updated over 8 years ago by StephenH

    2 replies • 15410 views
  • Discussion

    [SV] Constraint solver issue

    Category: Functional Verification

    By stanzani stanzani

    •

    updated over 8 years ago by TAM1

    1 replies • 18175 views
  • Discussion

    [AHB eVC]How to send transfers with no IDLE cycles

    Category: Functional Verification

    By J1EM1N J1EM1N

    •

    updated over 8 years ago by J1EM1N

    1 replies • 1174 views
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