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Functional Verification

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  • Discussion

    How to probe and view the variable wave in class?

    Category: Functional Verification

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    updated over 19 years ago by archive

    3 replies • 22773 views
  • Discussion

    parsing the arguments from command line

    Category: Functional Verification

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    updated over 19 years ago by archive

    3 replies • 23332 views
  • Discussion

    Come see the URM in action on May 2

    Category: Functional Verification

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    started over 19 years ago

    0 replies • 14180 views
  • Discussion

    Passing e defines through Model Sim

    Category: Functional Verification

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    updated over 19 years ago by archive

    2 replies • 15768 views
  • Discussion

    About URM library

    Category: Functional Verification

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    updated over 19 years ago by archive

    2 replies • 15345 views
  • Discussion

    C++ code through DPI?

    Category: Functional Verification

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    updated over 19 years ago by archive

    2 replies • 17594 views
  • Discussion

    SC-SV-Verilog interface

    Category: Functional Verification

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    started over 19 years ago

    0 replies • 14337 views
  • Discussion

    SC and SV co-simulation in IUS?

    Category: Functional Verification

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    updated over 19 years ago by archive

    3 replies • 16483 views
  • Discussion

    Reg : problem with reg declaration in IUS58

    Category: Functional Verification

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    updated over 19 years ago by archive

    4 replies • 16283 views
  • Discussion

    printf in IUS6.01

    Category: Functional Verification

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    updated over 19 years ago by archive

    6 replies • 17898 views
  • Discussion

    forall and endpoint/ended

    Category: Functional Verification

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    updated over 19 years ago by archive

    1 replies • 1468 views
  • Discussion

    Please update IPCM website

    Category: Functional Verification

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    updated over 19 years ago by archive

    2 replies • 15181 views
  • Discussion

    BFM written in class has to interface with phy signals

    Category: Functional Verification

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    updated over 19 years ago by archive

    16 replies • 27524 views
  • Discussion

    file I/O

    Category: Functional Verification

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    updated over 19 years ago by archive

    1 replies • 1354 views
  • Discussion

    generic task for hdl node force/release in system verilog

    Category: Functional Verification

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    updated over 19 years ago by archive

    1 replies • 3355 views
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