• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
CDNS - double leaderboard script

Functional Verification

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    waveform dump problem using SystemVerilog

    Category: Functional Verification

    By archive

    •

    updated over 19 years ago by archive

    6 replies • 22123 views
  • Discussion

    c routines used in specman

    Category: Functional Verification

    By archive

    •

    updated over 19 years ago by archive

    1 replies • 14824 views
  • Discussion

    Wand Wires to be driven by Program Block and Module block

    Category: Functional Verification

    By archive

    •

    updated over 19 years ago by archive

    10 replies • 20912 views
  • Discussion

    CDNLive! 2007: What will YOU be looking out for?

    Category: Functional Verification

    By archive

    •

    updated over 19 years ago by archive

    3 replies • 15545 views
  • Discussion

    Replication Patterns

    Category: Functional Verification

    By archive

    •

    updated over 19 years ago by archive

    6 replies • 18120 views
  • Discussion

    problem:: Functional coverage analysis

    Category: Functional Verification

    By archive

    •

    updated over 19 years ago by archive

    1 replies • 14858 views
  • Discussion

    vhdl & system verilog

    Category: Functional Verification

    By archive

    •

    updated over 19 years ago by archive

    10 replies • 11915 views
  • Discussion

    dynamic probes

    Category: Functional Verification

    By archive

    •

    updated over 19 years ago by archive

    3 replies • 16069 views
  • Discussion

    Check write only register functionality

    Category: Functional Verification

    By archive

    •

    updated over 19 years ago by archive

    1 replies • 16505 views
  • Discussion

    N unique stable data vectors

    Category: Functional Verification

    By archive

    •

    updated over 19 years ago by archive

    3 replies • 15893 views
  • Discussion

    Coverage on checks

    Category: Functional Verification

    By archive

    •

    updated over 19 years ago by archive

    1 replies • 14800 views
  • Discussion

    vhdl & system verilog

    Category: Functional Verification

    By archive

    •

    started over 19 years ago

    0 replies • 5806 views
  • Discussion

    Specman debug survey

    Category: Functional Verification

    By archive

    •

    updated over 19 years ago by archive

    1 replies • 14852 views
  • Discussion

    Verilog/SystemVerilog mixing ncsim Fatal error?

    Category: Functional Verification

    By archive

    •

    updated over 19 years ago by archive

    3 replies • 4394 views
  • Discussion

    forall and endpoint/ended

    Category: Functional Verification

    By archive

    •

    started over 19 years ago

    0 replies • 737 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information