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Functional Verification

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    vhdl & system verilog

    Category: Functional Verification

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    started over 18 years ago

    0 replies • 5507 views
  • Discussion

    Specman debug survey

    Category: Functional Verification

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    updated over 18 years ago by archive

    1 replies • 12973 views
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    Verilog/SystemVerilog mixing ncsim Fatal error?

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 3207 views
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    forall and endpoint/ended

    Category: Functional Verification

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    started over 18 years ago

    0 replies • 526 views
  • Discussion

    ENUM Types for StateMachines

    Category: Functional Verification

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    updated over 18 years ago by archive

    6 replies • 16422 views
  • Discussion

    interface for bidirectional pins

    Category: Functional Verification

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    updated over 18 years ago by archive

    1 replies • 13917 views
  • Discussion

    Hierarchical reference not allowed from within a package.

    Category: Functional Verification

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    updated over 18 years ago by archive

    5 replies • 22260 views
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    Using HAL

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 16019 views
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    ncelab: *F,INTERR: INTERNAL ERROR , debug

    Category: Functional Verification

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    updated over 18 years ago by archive

    4 replies • 3509 views
  • Discussion

    DPI and Classes

    Category: Functional Verification

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    updated over 18 years ago by archive

    4 replies • 16905 views
  • Discussion

    verilog user manua build-in functions guidel

    Category: Functional Verification

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    updated over 18 years ago by archive

    1 replies • 13086 views
  • Discussion

    Overloading $error in SVA under NCSIM

    Category: Functional Verification

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    updated over 18 years ago by archive

    6 replies • 16496 views
  • Discussion

    Multiple Classes per Package

    Category: Functional Verification

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    updated over 18 years ago by archive

    4 replies • 13611 views
  • Discussion

    DPI which can talk C++

    Category: Functional Verification

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    updated over 18 years ago by archive

    5 replies • 15736 views
  • Discussion

    Calling VHDL procedures in SystemVerilog Testbench.

    Category: Functional Verification

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    updated over 18 years ago by archive

    14 replies • 20004 views
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