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Functional Verification

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    HD Audio eVC/uVC

    Category: Functional Verification

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    started over 18 years ago

    0 replies • 440 views
  • Discussion

    IPCM question?

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    updated over 18 years ago by archive

    3 replies • 14700 views
  • Discussion

    Can I force or probe a signal in vhdl module from verilog top testbench?

    Category: Functional Verification

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    updated over 18 years ago by archive

    6 replies • 18350 views
  • Discussion

    How to tackle 'Aborted' properties.

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    updated over 18 years ago by archive

    3 replies • 6337 views
  • Discussion

    How frequently should Transactor work?

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    updated over 18 years ago by archive

    1 replies • 14062 views
  • Discussion

    Internal IUS error

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    updated over 18 years ago by archive

    7 replies • 17378 views
  • Discussion

    How to probe and view the variable wave in class?

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 20869 views
  • Discussion

    parsing the arguments from command line

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 20838 views
  • Discussion

    Come see the URM in action on May 2

    Category: Functional Verification

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    started over 18 years ago

    0 replies • 13170 views
  • Discussion

    Passing e defines through Model Sim

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    updated over 18 years ago by archive

    2 replies • 14432 views
  • Discussion

    About URM library

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    updated over 18 years ago by archive

    2 replies • 14041 views
  • Discussion

    C++ code through DPI?

    Category: Functional Verification

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    updated over 18 years ago by archive

    2 replies • 16173 views
  • Discussion

    SC-SV-Verilog interface

    Category: Functional Verification

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    started over 18 years ago

    0 replies • 13296 views
  • Discussion

    SC and SV co-simulation in IUS?

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 15025 views
  • Discussion

    Reg : problem with reg declaration in IUS58

    Category: Functional Verification

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    updated over 18 years ago by archive

    4 replies • 14872 views
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