Functional Verification

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Discussion

Possible to mix ncsim(64b) with DPI-C/C compiled in 32-bit address space?

Category: Functional Verification

By Ncsim User 1
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updated over 7 years ago by Ncsim User 1

1 replies • 1001 views
Discussion

How to accelerate ncelab phase when invoking irun?

Category: Functional Verification

By Jeff000
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updated over 7 years ago by sumg

4 replies • 2392 views
Discussion

Analyse the Functional Coverage of list of failing test case.

Category: Functional Verification

By sumg
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updated over 7 years ago by StephenH

6 replies • 17666 views
Discussion

How do I port a signal (reference data) from testbench to RTL module?

Category: Functional Verification

By Ncsim User 1
•
updated over 7 years ago by Ncsim User 1

2 replies • 13946 views
Discussion

Sort facility in Transaction Strip Chart

Category: Functional Verification

By Jeff000
•
started over 7 years ago

0 replies • 626 views
Discussion

Code coverage for sv verification envrionment

Category: Functional Verification

By Jeff000
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updated over 7 years ago by tpylant

2 replies • 2525 views
Discussion

Set -access +rw for regression

Category: Functional Verification

By PeterAF
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updated over 7 years ago by StephenH

1 replies • 1520 views
Discussion

ncvlog: *E,WKLNDF error

Category: Functional Verification

By TAZZMANIAN
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started over 7 years ago

0 replies • 1316 views
Discussion

How to get the preprocessor output from irun?

Category: Functional Verification

By Jeff000
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updated over 7 years ago by StephenH

7 replies • 5421 views
Discussion

NCSIM problem during functional simulation with Vivado

Category: Functional Verification

By anjo
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started over 7 years ago

0 replies • 12897 views
Discussion

Substitute instance in netlist with wrapper

Category: Functional Verification

By albas
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started over 7 years ago

0 replies • 13131 views
Discussion

False GLS timing violation being reported from irun for Functional D input in Scan mode

Category: Functional Verification

By bhanu27
•
updated over 7 years ago by bhanu27

1 replies • 13515 views
Discussion

ncelab and ncvlog version error conflict

Category: Functional Verification

By mhkvy4
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updated over 7 years ago by Adwaya

4 replies • 17932 views
Discussion

SystemVerilog "interface class"

Category: Functional Verification

By ChasL
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updated over 7 years ago by Tudor Timi

1 replies • 1701 views
Discussion

Issue related to use of cadence analog fetch function $cgav with a multi-bit analog signal

Category: Functional Verification

By bhanu27
•
started over 7 years ago

0 replies • 14227 views

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