Functional Verification

Latest Posts

Discussion

Cadence 17.2 Continuous Refresh problem

Category: Functional Verification

By ajeya
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updated over 8 years ago by StephenH

1 replies • 14953 views
Discussion

How to add hook when exit from simulation?

Category: Functional Verification

By Jeff000
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updated over 8 years ago by StephenH

3 replies • 1798 views
Discussion

C code generated by the veriloga

Category: Functional Verification

By PietroUser
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updated over 8 years ago by StephenH

1 replies • 15131 views
Discussion

How to get system time in SV?

Category: Functional Verification

By Jeff000
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updated over 8 years ago by Jeff000

2 replies • 7020 views
Discussion

iprof_report_dir generated with only a hidden folder

Category: Functional Verification

By Jeff000
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updated over 8 years ago by tpylant

1 replies • 1112 views
Discussion

How to increase the signal name font size in Simvision?

Category: Functional Verification

By Jeff000
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updated over 8 years ago by Jeff000

2 replies • 13202 views
Discussion

code_coverage_Error_The_design_unit _somename_has_multiple_top-level_instances_in_the_design_enabled_for_coverage

Category: Functional Verification

By MaheshKumar
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updated over 8 years ago by MaheshKumar

3 replies • 3511 views
Discussion

How to collapse and expand the group in simvision with tcl command?

Category: Functional Verification

By Jeff000
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updated over 8 years ago by Jeff000

2 replies • 4375 views
Discussion

How do I uncheck "Process statement" from sidebar in Simvision?

Category: Functional Verification

By Ncsim User 1
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updated over 8 years ago by StephenH

4 replies • 4147 views
Discussion

How do I add a compiled .a library to SV + DPI-C cosimulation?

Category: Functional Verification

By Ncsim User 1
•
updated over 8 years ago by Ncsim User 1

1 replies • 15112 views
Discussion

passing IRUN command-line arguments into vsif file?

Category: Functional Verification

By xzhao
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updated over 8 years ago by Subhash Sangam

4 replies • 23732 views
Discussion

Possible to mix ncsim(64b) with DPI-C/C compiled in 32-bit address space?

Category: Functional Verification

By Ncsim User 1
•
updated over 8 years ago by Ncsim User 1

1 replies • 1373 views
Discussion

How to accelerate ncelab phase when invoking irun?

Category: Functional Verification

By Jeff000
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updated over 8 years ago by sumg

4 replies • 3375 views
Discussion

Analyse the Functional Coverage of list of failing test case.

Category: Functional Verification

By sumg
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updated over 8 years ago by StephenH

6 replies • 21446 views
Discussion

How do I port a signal (reference data) from testbench to RTL module?

Category: Functional Verification

By Ncsim User 1
•
updated over 8 years ago by Ncsim User 1

2 replies • 16070 views

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