Functional Verification

How to add hook when exit from simulation?

Category: Functional Verification

C code generated by the veriloga

Category: Functional Verification

How to get system time in SV?

Category: Functional Verification

iprof_report_dir generated with only a hidden folder

Category: Functional Verification

How to increase the signal name font size in Simvision?

Category: Functional Verification

code_coverage_Error_The_design_unit _somename_has_multiple_top-level_instances_in_the_design_enabled_for_coverage

Category: Functional Verification

How to collapse and expand the group in simvision with tcl command?

Category: Functional Verification

How do I uncheck "Process statement" from sidebar in Simvision?

Category: Functional Verification

How do I add a compiled .a library to SV + DPI-C cosimulation?

Category: Functional Verification

passing IRUN command-line arguments into vsif file?

Category: Functional Verification

Possible to mix ncsim(64b) with DPI-C/C compiled in 32-bit address space?

Category: Functional Verification

How to accelerate ncelab phase when invoking irun?

Category: Functional Verification

Analyse the Functional Coverage of list of failing test case.

Category: Functional Verification

How do I port a signal (reference data) from testbench to RTL module?

Category: Functional Verification

Sort facility in Transaction Strip Chart

Category: Functional Verification