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Functional Verification

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  • Discussion

    ADDRESS Mapping issue in RAL in UVM

    Category: Functional Verification

    By mahee424

    •

    updated over 10 years ago by mahee424

    1 replies • 18563 views
  • Discussion

    HAL: turn on a rule in the design_info file

    Category: Functional Verification

    By maraninchijp

    •

    started over 10 years ago

    0 replies • 15220 views
  • Discussion

    Simvision plugin problem

    Category: Functional Verification

    By vinay1

    •

    updated over 10 years ago by vinay1

    1 replies • 15604 views
  • Discussion

    Gate level simulation flow with cadence

    Category: Functional Verification

    By sidharth1990

    •

    updated over 10 years ago by ReubenMijares

    1 replies • 15745 views
  • Discussion

    Covered in Formal

    Category: Functional Verification

    By sraghapx

    •

    started over 10 years ago

    0 replies • 14465 views
  • Discussion

    How to run a regression for multiple testcases with only a single compile using NCsim?

    Category: Functional Verification

    By ReubenMijares

    •

    updated over 10 years ago by cmarqu

    3 replies • 19763 views
  • Discussion

    licqueue is not working

    Category: Functional Verification

    By ReubenMijares

    •

    updated over 10 years ago by ReubenMijares

    3 replies • 20595 views
  • Discussion

    Jasper connectivity check

    Category: Functional Verification

    By sraghapx

    •

    updated over 10 years ago by sraghapx

    7 replies • 31688 views
  • Discussion

    Tutorial on NCsim

    Category: Functional Verification

    By ReubenMijares

    •

    updated over 10 years ago by StephenH

    5 replies • 38848 views
  • Discussion

    forcing signal to hierarchical connection in SystemVerilog when in interactive mode

    Category: Functional Verification

    By Almendrico

    •

    updated over 10 years ago by Almendrico

    4 replies • 21800 views
  • Discussion

    Missing symbols in UCIS shared library

    Category: Functional Verification

    By Abdulhamid

    •

    updated over 10 years ago by StephenH

    1 replies • 14997 views
  • Discussion

    bind procedure doesn't work if target VHDL unit is from a library

    Category: Functional Verification

    By Marius Ciurea

    •

    started over 10 years ago

    0 replies • 1826 views
  • Discussion

    how can i dump depth 1 level by $shm_probe

    Category: Functional Verification

    By JBPARK

    •

    started over 10 years ago

    0 replies • 14911 views
  • Discussion

    Several entity/architecture pairs for the the same cell?

    Category: Functional Verification

    By LuisGutierrez

    •

    started over 10 years ago

    0 replies • 675 views
  • Discussion

    Color highlighting SimVision's console

    Category: Functional Verification

    By freitas

    •

    updated over 10 years ago by Doug Koslow

    3 replies • 3439 views
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