Functional Verification

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Tutorial on NCsim

Category: Functional Verification

By ReubenMijares

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updated over 9 years ago by StephenH

5 replies • 35899 views
Discussion

forcing signal to hierarchical connection in SystemVerilog when in interactive mode

Category: Functional Verification

By Almendrico

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updated over 9 years ago by Almendrico

4 replies • 19548 views
Discussion

Missing symbols in UCIS shared library

Category: Functional Verification

By Abdulhamid

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updated over 9 years ago by StephenH

1 replies • 13862 views
Discussion

bind procedure doesn't work if target VHDL unit is from a library

Category: Functional Verification

By Marius Ciurea

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started over 9 years ago

0 replies • 1579 views
Discussion

how can i dump depth 1 level by $shm_probe

Category: Functional Verification

By JBPARK

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started over 9 years ago

0 replies • 13857 views
Discussion

Several entity/architecture pairs for the the same cell?

Category: Functional Verification

By LuisGutierrez

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started over 9 years ago

0 replies • 487 views
Discussion

Color highlighting SimVision's console

Category: Functional Verification

By freitas

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updated over 9 years ago by Doug Koslow

3 replies • 3026 views
Discussion

Viewing Verilog Tasks in Simvision

Category: Functional Verification

By tcatkins

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updated over 9 years ago by tcatkins

1 replies • 15211 views
Discussion

compilation error

Category: Functional Verification

By chandanc11

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started over 9 years ago

0 replies • 13358 views
Discussion

Any alternative way to connect an internal DUT's signals to TB's interface's modport?

Category: Functional Verification

By Rama Kishore

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updated over 9 years ago by Rama Kishore

2 replies • 6952 views
Discussion

IRUN command to change the Assertion severity level

Category: Functional Verification

By mahee424

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updated over 9 years ago by StephenH

5 replies • 20293 views
Discussion

cover property evaluation error

Category: Functional Verification

By mahee424

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updated over 9 years ago by mahee424

2 replies • 14823 views
Discussion

Query regarding the usage of analog assertions in systemverilog file

Category: Functional Verification

By susanta

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updated over 9 years ago by tpylant

6 replies • 17175 views
Discussion

Redirect Spectre results to buffer

Category: Functional Verification

By Khenglish

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updated over 9 years ago by Khenglish

2 replies • 14133 views
Discussion

Running Multiple Test Cases back to back (Regression)

Category: Functional Verification

By lijoostenk

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started over 9 years ago

0 replies • 14664 views

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