Functional Verification

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Discussion

Gate level simulation flow with cadence

Category: Functional Verification

By sidharth1990

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updated over 9 years ago by ReubenMijares

1 replies • 14950 views
Discussion

Covered in Formal

Category: Functional Verification

By sraghapx

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started over 9 years ago

0 replies • 13782 views
Discussion

How to run a regression for multiple testcases with only a single compile using NCsim?

Category: Functional Verification

By ReubenMijares

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updated over 9 years ago by cmarqu

3 replies • 18664 views
Discussion

licqueue is not working

Category: Functional Verification

By ReubenMijares

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updated over 9 years ago by ReubenMijares

3 replies • 19335 views
Discussion

Jasper connectivity check

Category: Functional Verification

By sraghapx

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updated over 9 years ago by sraghapx

7 replies • 28292 views
Discussion

Tutorial on NCsim

Category: Functional Verification

By ReubenMijares

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updated over 9 years ago by StephenH

5 replies • 36746 views
Discussion

forcing signal to hierarchical connection in SystemVerilog when in interactive mode

Category: Functional Verification

By Almendrico

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updated over 9 years ago by Almendrico

4 replies • 20137 views
Discussion

Missing symbols in UCIS shared library

Category: Functional Verification

By Abdulhamid

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updated over 9 years ago by StephenH

1 replies • 14225 views
Discussion

bind procedure doesn't work if target VHDL unit is from a library

Category: Functional Verification

By Marius Ciurea

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started over 9 years ago

0 replies • 1633 views
Discussion

how can i dump depth 1 level by $shm_probe

Category: Functional Verification

By JBPARK

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started over 9 years ago

0 replies • 14221 views
Discussion

Several entity/architecture pairs for the the same cell?

Category: Functional Verification

By LuisGutierrez

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started over 9 years ago

0 replies • 537 views
Discussion

Color highlighting SimVision's console

Category: Functional Verification

By freitas

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updated over 9 years ago by Doug Koslow

3 replies • 3108 views
Discussion

Viewing Verilog Tasks in Simvision

Category: Functional Verification

By tcatkins

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updated over 9 years ago by tcatkins

1 replies • 15627 views
Discussion

compilation error

Category: Functional Verification

By chandanc11

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started over 9 years ago

0 replies • 13701 views
Discussion

Any alternative way to connect an internal DUT's signals to TB's interface's modport?

Category: Functional Verification

By Rama Kishore

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updated over 9 years ago by Rama Kishore

2 replies • 7126 views

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