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Functional Verification

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  • Discussion

    simvision, get when a cover assertion was hit

    Category: Functional Verification

    By kkhsieh

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    updated over 9 years ago by kkhsieh

    4 replies • 15913 views
  • Discussion

    Hyperlinks for file and time using $display(), similar to uvm_info

    Category: Functional Verification

    By RenePi

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    started over 9 years ago

    0 replies • 14698 views
  • Discussion

    Simvision issue when representing an array of byes

    Category: Functional Verification

    By stanzani

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    started over 9 years ago

    0 replies • 14217 views
  • Discussion

    compare VerilogA result with SystemVerilog result

    Category: Functional Verification

    By NE555

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    updated over 9 years ago by NE555

    2 replies • 14674 views
  • Discussion

    NCSIM selective compile

    Category: Functional Verification

    By SimhanAnalog

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    updated over 9 years ago by SimhanAnalog

    2 replies • 16094 views
  • Discussion

    ncelab: *F,DLNOLK: Failed to get a exclusive lock on library ...

    Category: Functional Verification

    By petgusta

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    updated over 9 years ago by StephenH

    1 replies • 5639 views
  • Discussion

    NCSim 15.10 fails to execute VPI function

    Category: Functional Verification

    By FabianOboril

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    updated over 9 years ago by StephenH

    1 replies • 16648 views
  • Discussion

    How to make *E to flag as UVM_ERROR

    Category: Functional Verification

    By ReubenMijares

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    updated over 9 years ago by StephenH

    1 replies • 16372 views
  • Discussion

    How to run multiple tests in parallel

    Category: Functional Verification

    By ReubenMijares

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    •

    updated over 9 years ago by tpylant

    3 replies • 17723 views
  • Discussion

    Command that does not consider the coverage of a failing test to the coverage record

    Category: Functional Verification

    By ReubenMijares

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    updated over 9 years ago by StephenH

    1 replies • 14992 views
  • Discussion

    Post place-and-route SDF back-annotation fails when using Verilog multi-dimension array ports and internal nets

    Category: Functional Verification

    By Pacher Luca

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    updated over 9 years ago by Pacher Luca

    1 replies • 16145 views
  • Discussion

    Iterator Index Query is having a compile error

    Category: Functional Verification

    By ReubenMijares

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    updated over 9 years ago by ReubenMijares

    2 replies • 14572 views
  • Discussion

    ADDRESS Mapping issue in RAL in UVM

    Category: Functional Verification

    By mahee424

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    updated over 9 years ago by mahee424

    1 replies • 17580 views
  • Discussion

    HAL: turn on a rule in the design_info file

    Category: Functional Verification

    By maraninchijp

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    started over 9 years ago

    0 replies • 14504 views
  • Discussion

    Simvision plugin problem

    Category: Functional Verification

    By vinay1

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    •

    updated over 9 years ago by vinay1

    1 replies • 14764 views
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