Functional Verification

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Discussion

Capacitor model SystemVerilog

Category: Functional Verification

By NE555

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updated over 9 years ago by ronvogelsong

8 replies • 24363 views
Discussion

Simulator ignores attributes during elaboration

Category: Functional Verification

By FormerMember

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started over 9 years ago

0 replies • 3300 views
Discussion

Waveform of task in class?

Category: Functional Verification

By archive

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updated over 9 years ago by StephenH

2 replies • 14924 views
Discussion

What is FUNTSK? A fun task?

Category: Functional Verification

By SysTom

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updated over 9 years ago by StephenH

2 replies • 14771 views
Discussion

Influencing the mapping process

Category: Functional Verification

By Implophant

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started over 9 years ago

0 replies • 13244 views
Discussion

UVM variables in waveform aren't displayed instantly

Category: Functional Verification

By RenePi

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updated over 9 years ago by RenePi

1 replies • 2464 views
Discussion

simvision: how to add all signals in design to waves

Category: Functional Verification

By SysTom

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updated over 9 years ago by SysTom

4 replies • 24934 views
Discussion

Tool for tracing x propagation

Category: Functional Verification

By ReubenMijares

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started over 9 years ago

0 replies • 13407 views
Discussion

Adding -xprop option causes license issue

Category: Functional Verification

By ReubenMijares

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updated over 9 years ago by ReubenMijares

2 replies • 3992 views
Discussion

Create System Verilog library

Category: Functional Verification

By NE555

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started over 9 years ago

0 replies • 14383 views
Discussion

simvision, get when a cover assertion was hit

Category: Functional Verification

By kkhsieh

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updated over 9 years ago by kkhsieh

4 replies • 15518 views
Discussion

Hyperlinks for file and time using $display(), similar to uvm_info

Category: Functional Verification

By RenePi

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started over 9 years ago

0 replies • 14341 views
Discussion

Simvision issue when representing an array of byes

Category: Functional Verification

By stanzani

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started over 9 years ago

0 replies • 13871 views
Discussion

compare VerilogA result with SystemVerilog result

Category: Functional Verification

By NE555

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updated over 9 years ago by NE555

2 replies • 14308 views
Discussion

NCSIM selective compile

Category: Functional Verification

By SimhanAnalog

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updated over 9 years ago by SimhanAnalog

2 replies • 15689 views

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