Functional Verification

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ERROR : Object found for name dut.register but language domain is not supported !!

Category: Functional Verification

By zoombarabar

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updated over 9 years ago by zoombarabar

4 replies • 17564 views
Discussion

Regression Testing in UVM

Category: Functional Verification

By Eliz

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updated over 9 years ago by Eliz

2 replies • 17406 views
Discussion

ncelab: *E, CUVPOM: Port name '{*Name Protected*}' is invalid or has multiple conections

Category: Functional Verification

By Jyaray

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updated over 9 years ago by StephenH

1 replies • 10460 views
Discussion

Transition model of the hardware design by Cadence IFV

Category: Functional Verification

By RAJGD

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updated over 10 years ago by RAJGD

2 replies • 14205 views
Discussion

Reg: generating a .vsif file before running a regression in vManager 15.10

Category: Functional Verification

By Shobith

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updated over 10 years ago by StephenH

3 replies • 22247 views
Discussion

Error of undeclared identifier while calling c-function in VHDL with ncsim

Category: Functional Verification

By jayvyas13

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updated over 10 years ago by StephenH

1 replies • 15303 views
Discussion

Simulation in NCSIM

Category: Functional Verification

By Eliz

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updated over 10 years ago by StephenH

1 replies • 14918 views
Discussion

Error in Elaboration in UVM environment

Category: Functional Verification

By sunil kr

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updated over 10 years ago by Beth tamm

6 replies • 27598 views
Discussion

Verification of connectivity at top-level

Category: Functional Verification

By batari123

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updated over 10 years ago by ckomar

1 replies • 14028 views
Discussion

Using EEnet in SystemVerilog models

Category: Functional Verification

By Robert Peruzzi

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updated over 10 years ago by Robert Peruzzi

6 replies • 24975 views
Discussion

Need help in Verilog file creation

Category: Functional Verification

By mahee424

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updated over 10 years ago by mahee424

1 replies • 13972 views
Discussion

Spectre processes sleep for random interval

Category: Functional Verification

By Khenglish

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started over 10 years ago

0 replies • 13459 views
Discussion

Setting variable value from command line

Category: Functional Verification

By mahee424

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started over 10 years ago

0 replies • 13362 views
Discussion

How to make verilog function calls from non-DPI C model ?

Category: Functional Verification

By YHLiu

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started over 10 years ago

0 replies • 15378 views
Discussion

Setting up simulation for UVM

Category: Functional Verification

By Heisenberg

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updated over 10 years ago by tpylant

1 replies • 16229 views

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