Functional Verification

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Forcing Verilog signal simple_port with pli_access == TRUE in Specman

Category: Functional Verification

By mjzintc

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updated over 10 years ago by mjzintc

4 replies • 17154 views
Discussion

Whether DPI - C functions can be used in the environment where the top is in C.

Category: Functional Verification

By Vimala

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updated over 10 years ago by arnabd88

2 replies • 1912 views
Discussion

Generating a verilog netlist

Category: Functional Verification

By DhavalShah

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updated over 10 years ago by Anonymous

1 replies • 14634 views
Discussion

debug when model violates the TLM 2.0 base protocol

Category: Functional Verification

By ciroceissler

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started over 10 years ago

0 replies • 13202 views
Discussion

VHDL sensitivity list checking in Incisive

Category: Functional Verification

By CaveSpiderTech

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updated over 10 years ago by CaveSpiderTech

2 replies • 14587 views
Discussion

SystemC Verification float representation using integer constraints

Category: Functional Verification

By FormerMember

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started over 10 years ago

0 replies • 4614 views
Discussion

"SVSEED set from command line" does not appear in log file.

Category: Functional Verification

By bgpradeep

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updated over 10 years ago by Selvavinayak

1 replies • 1600 views
Discussion

Controlling Seed to multi langauge verification environment

Category: Functional Verification

By jaichandra

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updated over 10 years ago by jaichandra

5 replies • 15540 views
Discussion

IFV connectivity Check failure debug

Category: Functional Verification

By rajuchavan1

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updated over 10 years ago by rajuchavan1

4 replies • 15043 views
Discussion

Convergence Problem

Category: Functional Verification

By ANALOG DES

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updated over 10 years ago by ANALOG DES

1 replies • 14863 views
Discussion

HAL lint check design_info file

Category: Functional Verification

By zeoshin

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updated over 10 years ago by StephenH

1 replies • 17121 views
Discussion

UVM Monitor Help!!!

Category: Functional Verification

By Nhatt

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updated over 10 years ago by StephenH

1 replies • 14522 views
Discussion

[HELP] Error on cosimulation of VHDL and SystemC with e testbench

Category: Functional Verification

By Vinicius Alves

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updated over 10 years ago by hannes

4 replies • 15659 views
Discussion

DMS UVC Components

Category: Functional Verification

By andersonsv

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updated over 10 years ago by andersonsv

2 replies • 15058 views
Discussion

e generation question

Category: Functional Verification

By myonlyscreen

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updated over 10 years ago by hannes

1 replies • 13626 views

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