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Functional Verification

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  • Discussion

    Error in Elaboration in UVM environment

    Category: Functional Verification

    By sunil kr

    •

    updated over 10 years ago by Beth tamm

    6 replies • 29625 views
  • Discussion

    Verification of connectivity at top-level

    Category: Functional Verification

    By batari123

    •

    updated over 10 years ago by ckomar

    1 replies • 15195 views
  • Discussion

    Using EEnet in SystemVerilog models

    Category: Functional Verification

    By Robert Peruzzi

    •

    updated over 10 years ago by Robert Peruzzi

    6 replies • 27604 views
  • Discussion

    Need help in Verilog file creation

    Category: Functional Verification

    By mahee424

    •

    updated over 10 years ago by mahee424

    1 replies • 15069 views
  • Discussion

    Spectre processes sleep for random interval

    Category: Functional Verification

    By Khenglish

    •

    started over 10 years ago

    0 replies • 14616 views
  • Discussion

    Setting variable value from command line

    Category: Functional Verification

    By mahee424

    •

    started over 10 years ago

    0 replies • 14374 views
  • Discussion

    How to make verilog function calls from non-DPI C model ?

    Category: Functional Verification

    By YHLiu

    •

    started over 10 years ago

    0 replies • 16803 views
  • Discussion

    Setting up simulation for UVM

    Category: Functional Verification

    By Heisenberg

    •

    updated over 10 years ago by tpylant

    1 replies • 17547 views
  • Discussion

    Forcing Verilog signal simple_port with pli_access == TRUE in Specman

    Category: Functional Verification

    By mjzintc

    •

    updated over 10 years ago by mjzintc

    4 replies • 18911 views
  • Discussion

    Whether DPI - C functions can be used in the environment where the top is in C.

    Category: Functional Verification

    By Vimala

    •

    updated over 10 years ago by arnabd88

    2 replies • 2385 views
  • Discussion

    Generating a verilog netlist

    Category: Functional Verification

    By DhavalShah

    •

    updated over 11 years ago by Anonymous

    1 replies • 15779 views
  • Discussion

    debug when model violates the TLM 2.0 base protocol

    Category: Functional Verification

    By ciroceissler

    •

    started over 11 years ago

    0 replies • 14191 views
  • Discussion

    VHDL sensitivity list checking in Incisive

    Category: Functional Verification

    By CaveSpiderTech

    •

    updated over 11 years ago by CaveSpiderTech

    2 replies • 15860 views
  • Discussion

    SystemC Verification float representation using integer constraints

    Category: Functional Verification

    By FormerMember

    •

    started over 11 years ago

    0 replies • 4747 views
  • Discussion

    "SVSEED set from command line" does not appear in log file.

    Category: Functional Verification

    By bgpradeep

    •

    updated over 11 years ago by Selvavinayak

    1 replies • 1887 views
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