• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
CDNS - double leaderboard script

Functional Verification

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    IFV and IUS, what's the difference?

    Category: Functional Verification

    By archive

    •

    updated over 13 years ago by GAO SHIYANG

    7 replies • 6754 views
  • Discussion

    IUS 10.2 irun - how to re-run an already compiled snapshot

    Category: Functional Verification

    By cubicle82

    •

    updated over 13 years ago by GAO SHIYANG

    8 replies • 14282 views
  • Discussion

    Super Linting advantages

    Category: Functional Verification

    By Buvna

    •

    started over 13 years ago

    0 replies • 14578 views
  • Discussion

    Can I replace the test pattern after restart the snapshot

    Category: Functional Verification

    By happydog

    •

    started over 13 years ago

    0 replies • 14277 views
  • Discussion

    how to create System C Wrapper over system verilog..

    Category: Functional Verification

    By RAMANATHAN CT

    •

    started over 13 years ago

    0 replies • 14772 views
  • Discussion

    what do you mean by assertion block

    Category: Functional Verification

    By BharathECE

    •

    updated over 13 years ago by maheshs

    1 replies • 15480 views
  • Discussion

    convert string to list of bit

    Category: Functional Verification

    By mmbr

    •

    updated over 13 years ago by mmbr

    2 replies • 15899 views
  • Discussion

    SystemVerilog Assertions: Property Library

    Category: Functional Verification

    By Paulo Pinzani

    •

    started over 13 years ago

    0 replies • 15239 views
  • Discussion

    how to Simulate SystemC file...

    Category: Functional Verification

    By Selvavinayak

    •

    updated over 13 years ago by muffi

    1 replies • 16657 views
  • Discussion

    Trace fail

    Category: Functional Verification

    By Buvna

    •

    updated over 13 years ago by TAM1

    3 replies • 15683 views
  • Discussion

    Questions about IFV - PLS Help! - New to IFV

    Category: Functional Verification

    By alexlop

    •

    updated over 13 years ago by Kris4Rad

    15 replies • 8069 views
  • Discussion

    how to reduce explored

    Category: Functional Verification

    By BharathECE

    •

    updated over 13 years ago by Buvna

    4 replies • 16709 views
  • Discussion

    SOC connectivity checks

    Category: Functional Verification

    By Buvna

    •

    updated over 13 years ago by Buvna

    1 replies • 15052 views
  • Discussion

    AFA for VHDL in IFV

    Category: Functional Verification

    By Buvna

    •

    updated over 13 years ago by Buvna

    2 replies • 15098 views
  • Discussion

    which all signals need to be initialized in a module

    Category: Functional Verification

    By BharathECE

    •

    updated over 13 years ago by BharathECE

    2 replies • 15393 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information