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Functional Verification

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  • Discussion

    Switch to run through assertions

    Category: Functional Verification

    By Teeeravis Teeeravis

    •

    updated over 12 years ago by tpylant

    3 replies • 17583 views
  • Discussion

    How to match the UVC version & the cdn_e_utils version

    Category: Functional Verification

    By giridhara giridhara

    •

    started over 12 years ago

    0 replies • 595 views
  • Discussion

    time between two events

    Category: Functional Verification

    By pravintavagad pravintavagad

    •

    updated over 12 years ago by StephenH

    4 replies • 14871 views
  • Discussion

    list generation

    Category: Functional Verification

    By guyl guyl

    •

    updated over 12 years ago by hannes

    1 replies • 13089 views
  • Discussion

    print all the `defines

    Category: Functional Verification

    By dechaoz05 dechaoz05

    •

    updated over 12 years ago by hannes

    1 replies • 13889 views
  • Discussion

    How to filter X -> 0 or X -> 1 from signals for events

    Category: Functional Verification

    By jaichandra jaichandra

    •

    updated over 12 years ago by hannes

    3 replies • 1388 views
  • Discussion

    XBus XSoC XSerial examples

    Category: Functional Verification

    By pravintavagad pravintavagad

    •

    updated over 12 years ago by hannes

    1 replies • 13103 views
  • Discussion

    passing events as parameters to methods or TCM

    Category: Functional Verification

    By jaichandra jaichandra

    •

    updated over 12 years ago by hannes

    1 replies • 12936 views
  • Discussion

    SystemVerilog modport question

    Category: Functional Verification

    By SCollins SCollins

    •

    updated over 12 years ago by SCollins

    2 replies • 17116 views
  • Discussion

    Use of a specify block within a SystemVerilog interface

    Category: Functional Verification

    By SCollins SCollins

    •

    updated over 12 years ago by SCollins

    1 replies • 17299 views
  • Discussion

    irun 11.10-s062 -R option and *W,WKWTLK "Waiting for a Exclusive lock"

    Category: Functional Verification

    By cubicle82 cubicle82

    •

    started over 12 years ago

    0 replies • 3060 views
  • Discussion

    Generation of EVCD file for Verilog-AMS

    Category: Functional Verification

    By Anky Anky

    •

    started over 12 years ago

    0 replies • 14713 views
  • Discussion

    Any symbol for simulation of mutual induction between two inductors?

    Category: Functional Verification

    By Abhimanyu1 Abhimanyu1

    •

    started over 12 years ago

    0 replies • 13257 views
  • Discussion

    comparing a signal length

    Category: Functional Verification

    By vijay828 vijay828

    •

    started over 12 years ago

    0 replies • 12680 views
  • Discussion

    CONFORMAL LEC-NON EQUIVALENT BLACK BOXES

    Category: Functional Verification

    By SWAROOP24X7 SWAROOP24X7

    •

    started over 12 years ago

    0 replies • 14685 views
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