Functional Verification

Latest Posts

Discussion

Concatenating enumerated types in coverpoint

Category: Functional Verification

By RajeshCM
•
updated over 12 years ago by tpylant

4 replies • 15783 views
Discussion

Looking for help with System Verilog in AMS

Category: Functional Verification

By JRAHildebrand
•
updated over 13 years ago by Shalom B

12 replies • 18801 views
Discussion

Need help when using the AMS-Ultrasim tools,occuring some problems in Electrical signal to Logical signal connect module

Category: Functional Verification

By zhangyz
•
started over 13 years ago

0 replies • 396 views
Discussion

tk plugin error in ncsim

Category: Functional Verification

By NormanW
•
updated over 13 years ago by StephenH

1 replies • 13487 views
Discussion

How to apply Dynamic Load and Reseed Methodology into UVM

Category: Functional Verification

By clacasse
•
started over 13 years ago

0 replies • 12875 views
Discussion

Re: How to Simulate 64-bit VHDL Code in Cadence?

Category: Functional Verification

By grasshopper
•
started over 13 years ago

0 replies • 12619 views
Discussion

How to save the signals in waveform window?

Category: Functional Verification

By rohslogic
•
updated over 13 years ago by TAM1

1 replies • 26859 views
Discussion

Internal error during elabration phase

Category: Functional Verification

By mdkaleem
•
updated over 13 years ago by mdkaleem

6 replies • 15319 views
Discussion

IMC Coverage

Category: Functional Verification

By MDK1234
•
updated over 13 years ago by StephenH

3 replies • 21508 views
Discussion

Forcing a VHDL signal from a Verilog Test/Env

Category: Functional Verification

By ashfaqh
•
updated over 13 years ago by ravisguptaji

4 replies • 7128 views
Discussion

cannot use $cds_analog_exists() or $cgav()

Category: Functional Verification

By freitas
•
updated over 13 years ago by freitas

1 replies • 13966 views
Discussion

ncverilog simulation verilog: error fmuk

Category: Functional Verification

By weebey
•
updated over 13 years ago by weebey

5 replies • 25605 views
Discussion

simvision plugins - tcl tk 8.5? tcl 8.4 tile? c++ qt?

Category: Functional Verification

By tomers
•
updated over 13 years ago by Doug Koslow

3 replies • 1973 views
Discussion

"INTERNAL EXCEPTION" when ncsim

Category: Functional Verification

By Tommy zou
•
started over 13 years ago

0 replies • 3131 views
Discussion

Using interface signals as coverpoint bins

Category: Functional Verification

By RajeshCM
•
updated over 13 years ago by TAM1

1 replies • 15851 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.