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Functional Verification

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  • Discussion

    How to filter X -> 0 or X -> 1 from signals for events

    Category: Functional Verification

    By jaichandra

    •

    updated over 13 years ago by hannes

    3 replies • 1976 views
  • Discussion

    XBus XSoC XSerial examples

    Category: Functional Verification

    By pravintavagad

    •

    updated over 13 years ago by hannes

    1 replies • 14890 views
  • Discussion

    passing events as parameters to methods or TCM

    Category: Functional Verification

    By jaichandra

    •

    updated over 13 years ago by hannes

    1 replies • 14750 views
  • Discussion

    SystemVerilog modport question

    Category: Functional Verification

    By SCollins

    •

    updated over 13 years ago by SCollins

    2 replies • 20649 views
  • Discussion

    Use of a specify block within a SystemVerilog interface

    Category: Functional Verification

    By SCollins

    •

    updated over 13 years ago by SCollins

    1 replies • 20113 views
  • Discussion

    irun 11.10-s062 -R option and *W,WKWTLK "Waiting for a Exclusive lock"

    Category: Functional Verification

    By cubicle82

    •

    started over 13 years ago

    0 replies • 3617 views
  • Discussion

    Generation of EVCD file for Verilog-AMS

    Category: Functional Verification

    By Anky

    •

    started over 13 years ago

    0 replies • 16610 views
  • Discussion

    Any symbol for simulation of mutual induction between two inductors?

    Category: Functional Verification

    By Abhimanyu1

    •

    started over 14 years ago

    0 replies • 14985 views
  • Discussion

    comparing a signal length

    Category: Functional Verification

    By vijay828

    •

    started over 14 years ago

    0 replies • 14352 views
  • Discussion

    CONFORMAL LEC-NON EQUIVALENT BLACK BOXES

    Category: Functional Verification

    By SWAROOP24X7

    •

    started over 14 years ago

    0 replies • 17100 views
  • Discussion

    Concatenating enumerated types in coverpoint

    Category: Functional Verification

    By RajeshCM

    •

    updated over 14 years ago by tpylant

    4 replies • 18177 views
  • Discussion

    Looking for help with System Verilog in AMS

    Category: Functional Verification

    By JRAHildebrand

    •

    updated over 14 years ago by Shalom B

    12 replies • 22953 views
  • Discussion

    Need help when using the AMS-Ultrasim tools,occuring some problems in Electrical signal to Logical signal connect module

    Category: Functional Verification

    By zhangyz

    •

    started over 14 years ago

    0 replies • 615 views
  • Discussion

    tk plugin error in ncsim

    Category: Functional Verification

    By NormanW

    •

    updated over 14 years ago by StephenH

    1 replies • 15390 views
  • Discussion

    How to apply Dynamic Load and Reseed Methodology into UVM

    Category: Functional Verification

    By clacasse

    •

    started over 14 years ago

    0 replies • 14544 views
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