Functional Verification

Latest Posts

Discussion

How to apply Dynamic Load and Reseed Methodology into UVM

Category: Functional Verification

By clacasse
•
started over 14 years ago

0 replies • 14570 views
Discussion

Re: How to Simulate 64-bit VHDL Code in Cadence?

Category: Functional Verification

By grasshopper
•
started over 14 years ago

0 replies • 14248 views
Discussion

How to save the signals in waveform window?

Category: Functional Verification

By rohslogic
•
updated over 14 years ago by TAM1

1 replies • 31395 views
Discussion

Internal error during elabration phase

Category: Functional Verification

By mdkaleem
•
updated over 14 years ago by mdkaleem

6 replies • 17953 views
Discussion

IMC Coverage

Category: Functional Verification

By MDK1234
•
updated over 14 years ago by StephenH

3 replies • 24722 views
Discussion

Forcing a VHDL signal from a Verilog Test/Env

Category: Functional Verification

By ashfaqh
•
updated over 14 years ago by ravisguptaji

4 replies • 8872 views
Discussion

cannot use $cds_analog_exists() or $cgav()

Category: Functional Verification

By freitas
•
updated over 14 years ago by freitas

1 replies • 15941 views
Discussion

ncverilog simulation verilog: error fmuk

Category: Functional Verification

By weebey
•
updated over 14 years ago by weebey

5 replies • 29049 views
Discussion

simvision plugins - tcl tk 8.5? tcl 8.4 tile? c++ qt?

Category: Functional Verification

By tomers
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updated over 14 years ago by Doug Koslow

3 replies • 2935 views
Discussion

"INTERNAL EXCEPTION" when ncsim

Category: Functional Verification

By Tommy zou
•
started over 14 years ago

0 replies • 3693 views
Discussion

Using interface signals as coverpoint bins

Category: Functional Verification

By RajeshCM
•
updated over 14 years ago by TAM1

1 replies • 18042 views
Discussion

Verification Plan using Eplanner

Category: Functional Verification

By Manish Verma
•
updated over 14 years ago by StephenH

19 replies • 25482 views
Discussion

Using Eplanner with UVM

Category: Functional Verification

By rdalibor
•
updated over 14 years ago by rdalibor

2 replies • 15962 views
Discussion

help needed on the use Scemi2.0 Pipe between OVM tb and HDL

Category: Functional Verification

By Xinwei
•
updated over 14 years ago by Xinwei

3 replies • 16027 views
Discussion

NC_MIRROR help

Category: Functional Verification

By Aqeel
•
updated over 14 years ago by Aqeel

2 replies • 17290 views

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