Functional Verification

Latest Posts

Discussion

cross coverage between different bits in register and different bits in different register

Category: Functional Verification

By archvasu

$usertype
•
updated over 14 years ago by StephenH

1 replies • 14863 views
Discussion

Error: ncelab: *F,CUATOP: Attempt to instance top level module

Category: Functional Verification

By Lawee

$usertype
•
updated over 14 years ago by TAM1

1 replies • 2556 views
Discussion

write a single assertions with constraints embedded

Category: Functional Verification

By Ashish Goel

$usertype
•
updated over 14 years ago by Ashish Goel

2 replies • 14266 views
Discussion

:)

Category: Functional Verification

By Rupinder

$usertype
•
updated over 14 years ago by TAM1

1 replies • 596 views
Discussion

DPI-C Simulation error

Category: Functional Verification

By Miguel Caetano

$usertype
•
updated over 14 years ago by Vishnugupt

3 replies • 6784 views
Discussion

Reading input files

Category: Functional Verification

By EveBell

$usertype
•
updated over 14 years ago by EveBell

2 replies • 14726 views
Discussion

Simulation halt: NC-Verilog

Category: Functional Verification

By Seokhyeong

$usertype
•
updated over 14 years ago by TAM1

1 replies • 14999 views
Discussion

class casting

Category: Functional Verification

By arjuny

$usertype
•
updated over 14 years ago by jadec

1 replies • 13974 views
Discussion

pull mode vs push mode

Category: Functional Verification

By onkarkk

$usertype
•
updated over 14 years ago by jadec

5 replies • 20502 views
Discussion

vplan in xls format

Category: Functional Verification

By nirmit shah

$usertype
•
updated over 14 years ago by pcarzola

3 replies • 18489 views
Discussion

does IUS8106 version supports system verilog code or syntax

Category: Functional Verification

By nirmit shah

$usertype
•
updated over 14 years ago by nirmit shah

2 replies • 14297 views
Discussion

CTL model checking in Cadence SMV

Category: Functional Verification

By amirhossein

$usertype
•
started over 14 years ago

0 replies • 14108 views
Discussion

Temporal expression

Category: Functional Verification

By MVSI

$usertype
•
started over 14 years ago

0 replies • 13728 views
Discussion

System Verilog rule file for HAL

Category: Functional Verification

By diablo

$usertype
•
updated over 14 years ago by diablo

2 replies • 16357 views
Discussion

how to write formal assertion for mentioned property

Category: Functional Verification

By Ashish Goel

$usertype
•
started over 14 years ago

0 replies • 13720 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.