Functional Verification

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Discussion

Error when combining AXI UVC and AHB UVC

Category: Functional Verification

By Louis Gao
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updated over 15 years ago by Louis Gao

2 replies • 16464 views
Discussion

How to model the following twisted pair cable in PSPICE? Help ASAP

Category: Functional Verification

By archive
•
updated over 15 years ago by Alok Tripathi

1 replies • 16071 views
Discussion

I need a PSPICE model for a Litium Ion battery - 8s32p

Category: Functional Verification

By archive
•
updated over 15 years ago by Alok Tripathi

1 replies • 2990 views
Discussion

Sequences from within other sequences of different type

Category: Functional Verification

By hailesen
•
updated over 15 years ago by hailesen

2 replies • 15738 views
Discussion

cross coverage between different bits in register and different bits in different register

Category: Functional Verification

By archvasu
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updated over 15 years ago by StephenH

1 replies • 15733 views
Discussion

Error: ncelab: *F,CUATOP: Attempt to instance top level module

Category: Functional Verification

By Lawee
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updated over 15 years ago by TAM1

1 replies • 2872 views
Discussion

write a single assertions with constraints embedded

Category: Functional Verification

By Ashish Goel
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updated over 15 years ago by Ashish Goel

2 replies • 15098 views
Discussion

:)

Category: Functional Verification

By Rupinder
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updated over 15 years ago by TAM1

1 replies • 768 views
Discussion

DPI-C Simulation error

Category: Functional Verification

By Miguel Caetano
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updated over 15 years ago by Vishnugupt

3 replies • 7381 views
Discussion

Reading input files

Category: Functional Verification

By EveBell
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updated over 15 years ago by EveBell

2 replies • 15586 views
Discussion

Simulation halt: NC-Verilog

Category: Functional Verification

By Seokhyeong
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updated over 15 years ago by TAM1

1 replies • 15777 views
Discussion

class casting

Category: Functional Verification

By arjuny
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updated over 15 years ago by jadec

1 replies • 14761 views
Discussion

pull mode vs push mode

Category: Functional Verification

By onkarkk
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updated over 15 years ago by jadec

5 replies • 22601 views
Discussion

vplan in xls format

Category: Functional Verification

By nirmit shah
•
updated over 15 years ago by pcarzola

3 replies • 19925 views
Discussion

does IUS8106 version supports system verilog code or syntax

Category: Functional Verification

By nirmit shah
•
updated over 15 years ago by nirmit shah

2 replies • 15145 views

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