Functional Verification

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Discussion

Configurable IO pins in SystemVerilog

Category: Functional Verification

By verifs
•
updated over 15 years ago by verifs

2 replies • 16705 views
Discussion

Data collection for expect and Checks

Category: Functional Verification

By nishvlsi2011
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updated over 15 years ago by StephenH

1 replies • 14707 views
Discussion

Const ref queue as function argument

Category: Functional Verification

By sperrotta
•
started over 15 years ago

0 replies • 14235 views
Discussion

Do $shm_suspend and $shm_resume work?

Category: Functional Verification

By abiamb
•
updated over 15 years ago by TAM1

3 replies • 16652 views
Discussion

help with MONTE-CARLO, oceanxl script

Category: Functional Verification

By ronis
•
started over 15 years ago

0 replies • 14186 views
Discussion

Exclude functional coverage for particular test

Category: Functional Verification

By Ravisinha
•
updated over 15 years ago by StephenH

5 replies • 17781 views
Discussion

vr_ahb_tlm systemc model

Category: Functional Verification

By nishvlsi2011
•
updated over 15 years ago by abhineet22

4 replies • 15982 views
Discussion

VHDL 2008 force/release feature absent from ncvhdl

Category: Functional Verification

By mouyseb
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started over 15 years ago

0 replies • 2034 views
Discussion

cross cover issue ?

Category: Functional Verification

By Ashish Goel
•
started over 15 years ago

0 replies • 14371 views
Discussion

Can +ams and +sv options be used together in ncverilog

Category: Functional Verification

By Prachi1
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updated over 15 years ago by tpylant

1 replies • 15936 views
Discussion

Coverage on VAMS model

Category: Functional Verification

By Ashish Goel
•
started over 15 years ago

0 replies • 14321 views
Discussion

dependecy checking ----- Can anybody tell me how to approach for this problem

Category: Functional Verification

By Ashish Goel
•
updated over 15 years ago by Ashish Goel

2 replies • 1419 views
Discussion

How to pass arguments to ncsc_run just like you would pass arguments from the command line to a C program.

Category: Functional Verification

By Matthieu P
•
updated over 15 years ago by Matthieu P

2 replies • 16345 views
Discussion

Double back-tick in parametrized macro in SV

Category: Functional Verification

By sevent
•
updated over 15 years ago by jadec

7 replies • 24963 views
Discussion

How to use HAL to analyse VHDL files using unisim library?

Category: Functional Verification

By PowerfulBANG
•
started over 15 years ago

0 replies • 14497 views

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