Functional Verification

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Discussion

Using DPI to get the current value of a signal

Category: Functional Verification

By sdav

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updated over 15 years ago by sdav

3 replies • 17648 views
Discussion

.vp file simulate

Category: Functional Verification

By digimind4ever

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started over 15 years ago

0 replies • 14655 views
Discussion

a problem about ams simluation.

Category: Functional Verification

By phoenixson

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started over 15 years ago

0 replies • 13805 views
Discussion

Ignoring certain module during sdf annotation

Category: Functional Verification

By abhingp01

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started over 15 years ago

0 replies • 14499 views
Discussion

Referencing a VHDL signal from a Verilog Module

Category: Functional Verification

By ashfaqh

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updated over 15 years ago by tpylant

1 replies • 14872 views
Discussion

vr_ad_file multiple instance

Category: Functional Verification

By Ravisinha

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updated over 15 years ago by Ravisinha

4 replies • 16009 views
Discussion

help with e *** Error: list is empty - cannot access item 0

Category: Functional Verification

By JAbusaid

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updated over 15 years ago by StephenH

1 replies • 1511 views
Discussion

AXI eVC for 512-bit data width

Category: Functional Verification

By spark

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updated over 15 years ago by StephenH

1 replies • 14290 views
Discussion

General question/problem with Cadence

Category: Functional Verification

By Robak

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updated over 15 years ago by Robak

2 replies • 1005 views
Discussion

mixed language simulation

Category: Functional Verification

By josephbell

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updated over 15 years ago by jenkinrob

4 replies • 15948 views
Discussion

e tcm/event order

Category: Functional Verification

By DANDOOOOO

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started over 15 years ago

0 replies • 650 views
Discussion

A problem about Conformal

Category: Functional Verification

By Flyakite

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started over 15 years ago

0 replies • 13675 views
Discussion

VHDL Procedure Call from a Verilog Module

Category: Functional Verification

By ashfaqh

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started over 15 years ago

0 replies • 14073 views
Discussion

MixedLanguage (Verilog+VHDL) Question

Category: Functional Verification

By ashfaqh

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updated over 15 years ago by ashfaqh

4 replies • 2610 views
Discussion

Importing C Function into System Verilog using Incisive DPI

Category: Functional Verification

By random

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updated over 15 years ago by TAM1

1 replies • 15094 views

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