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Functional Verification

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  • Discussion

    Linux support for IC610?

    Category: Functional Verification

    By invar

    •

    updated over 16 years ago by invar

    2 replies • 15863 views
  • Discussion

    looking for advise on connecting to analog model

    Category: Functional Verification

    By myonlyscreen

    •

    updated over 16 years ago by myonlyscreen

    2 replies • 15141 views
  • Discussion

    Write, compile and simulate verilog/vhdl code in cadence

    Category: Functional Verification

    By Sambhav

    •

    started over 16 years ago

    0 replies • 1795 views
  • Discussion

    NCVHDL Compiler

    Category: Functional Verification

    By wolf82

    •

    started over 16 years ago

    0 replies • 15126 views
  • Discussion

    Using DPI to get the current value of a signal

    Category: Functional Verification

    By sdav

    •

    updated over 16 years ago by sdav

    3 replies • 19011 views
  • Discussion

    .vp file simulate

    Category: Functional Verification

    By digimind4ever

    •

    started over 16 years ago

    0 replies • 15363 views
  • Discussion

    a problem about ams simluation.

    Category: Functional Verification

    By phoenixson

    •

    started over 16 years ago

    0 replies • 14470 views
  • Discussion

    Ignoring certain module during sdf annotation

    Category: Functional Verification

    By abhingp01

    •

    started over 16 years ago

    0 replies • 15197 views
  • Discussion

    Referencing a VHDL signal from a Verilog Module

    Category: Functional Verification

    By ashfaqh

    •

    updated over 16 years ago by tpylant

    1 replies • 15641 views
  • Discussion

    vr_ad_file multiple instance

    Category: Functional Verification

    By Ravisinha

    •

    updated over 16 years ago by Ravisinha

    4 replies • 16957 views
  • Discussion

    help with e *** Error: list is empty - cannot access item 0

    Category: Functional Verification

    By JAbusaid

    •

    updated over 16 years ago by StephenH

    1 replies • 1736 views
  • Discussion

    AXI eVC for 512-bit data width

    Category: Functional Verification

    By spark

    •

    updated over 16 years ago by StephenH

    1 replies • 15076 views
  • Discussion

    General question/problem with Cadence

    Category: Functional Verification

    By Robak

    •

    updated over 16 years ago by Robak

    2 replies • 1257 views
  • Discussion

    mixed language simulation

    Category: Functional Verification

    By josephbell

    •

    updated over 16 years ago by jenkinrob

    4 replies • 17006 views
  • Discussion

    e tcm/event order

    Category: Functional Verification

    By DANDOOOOO

    •

    started over 16 years ago

    0 replies • 815 views
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