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Functional Verification

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  • Discussion

    NCVHDL Compiler

    Category: Functional Verification

    By wolf82

    •

    started over 15 years ago

    0 replies • 15079 views
  • Discussion

    Using DPI to get the current value of a signal

    Category: Functional Verification

    By sdav

    •

    updated over 15 years ago by sdav

    3 replies • 18818 views
  • Discussion

    .vp file simulate

    Category: Functional Verification

    By digimind4ever

    •

    started over 15 years ago

    0 replies • 15320 views
  • Discussion

    a problem about ams simluation.

    Category: Functional Verification

    By phoenixson

    •

    started over 15 years ago

    0 replies • 14428 views
  • Discussion

    Ignoring certain module during sdf annotation

    Category: Functional Verification

    By abhingp01

    •

    started over 15 years ago

    0 replies • 15146 views
  • Discussion

    Referencing a VHDL signal from a Verilog Module

    Category: Functional Verification

    By ashfaqh

    •

    updated over 15 years ago by tpylant

    1 replies • 15566 views
  • Discussion

    vr_ad_file multiple instance

    Category: Functional Verification

    By Ravisinha

    •

    updated over 15 years ago by Ravisinha

    4 replies • 16830 views
  • Discussion

    help with e *** Error: list is empty - cannot access item 0

    Category: Functional Verification

    By JAbusaid

    •

    updated over 15 years ago by StephenH

    1 replies • 1684 views
  • Discussion

    AXI eVC for 512-bit data width

    Category: Functional Verification

    By spark

    •

    updated over 15 years ago by StephenH

    1 replies • 15014 views
  • Discussion

    General question/problem with Cadence

    Category: Functional Verification

    By Robak

    •

    updated over 15 years ago by Robak

    2 replies • 1175 views
  • Discussion

    mixed language simulation

    Category: Functional Verification

    By josephbell

    •

    updated over 15 years ago by jenkinrob

    4 replies • 16860 views
  • Discussion

    e tcm/event order

    Category: Functional Verification

    By DANDOOOOO

    •

    started over 15 years ago

    0 replies • 754 views
  • Discussion

    A problem about Conformal

    Category: Functional Verification

    By Flyakite

    •

    started over 15 years ago

    0 replies • 14294 views
  • Discussion

    VHDL Procedure Call from a Verilog Module

    Category: Functional Verification

    By ashfaqh

    •

    started over 16 years ago

    0 replies • 14707 views
  • Discussion

    MixedLanguage (Verilog+VHDL) Question

    Category: Functional Verification

    By ashfaqh

    •

    updated over 16 years ago by ashfaqh

    4 replies • 2976 views
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