Logic Design

Latest Posts

Discussion

SystemVerilog package used inside VHDL-2008 design?

Category: Logic Design

By Michal Kajan
•
started over 5 years ago

0 replies • 14144 views
Discussion

How to customize default_hdl_checks/rules in CCD conformal constraint designer

Category: Logic Design

By mirzaaur
•
started over 6 years ago

0 replies • 1219 views
Discussion

using ModelSim/QuestaSim VCD file in RTL compiler

Category: Logic Design

By dkhan
•
updated over 6 years ago by shvd

4 replies • 6721 views
Discussion

Post-synthesis Simulation Failing when lp_insert_clock_gating true

Category: Logic Design

By GGobieski
•
updated over 6 years ago by GGobieski

1 replies • 14807 views
Discussion

Unable to map design without a suitable latch. [MAP-3] [synthesize]

Category: Logic Design

By 20050710212
•
updated over 6 years ago by wickjohn

6 replies • 21984 views
Discussion

Mouse wheel and [i][o] button doesn't zoom

Category: Logic Design

By phanvandung
•
started over 6 years ago

0 replies • 1374 views
Discussion

Reuse of Schematics across different Projects

Category: Logic Design

By akmo25
•
started over 6 years ago

0 replies • 13292 views
Discussion

stretching LOW pulse signal for extra 100ns

Category: Logic Design

By Iaf22
•
started over 6 years ago

0 replies • 13276 views
Discussion

Genus synthesis syntax Foreach

Category: Logic Design

By yann06
•
updated over 6 years ago by GeorgeGG

1 replies • 14379 views
Discussion

List of Highest Fanouts

Category: Logic Design

By GeorgeGG
•
started over 6 years ago

0 replies • 13061 views
Discussion

problem with "REPORT RULE CHECK" command using conformal

Category: Logic Design

By zohaibhassan
•
updated over 6 years ago by zohaibhassan

3 replies • 5222 views
Discussion

Conformal ECO use cell out of spare(NO_MAP)

Category: Logic Design

By Ben Xu
•
started over 6 years ago

0 replies • 1188 views
Discussion

CONFORMAL ECO : SPARE CELLS NOT MAPPED

Category: Logic Design

By NabilE
•
started over 6 years ago

0 replies • 13930 views
Discussion

functional equivalence check between system verilog and schematic

Category: Logic Design

By SatendraMaurya
•
started over 6 years ago

0 replies • 13475 views
Discussion

Formatting of concept HDL schematic pages

Category: Logic Design

By akmo25
•
started over 6 years ago

0 replies • 13172 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.