• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Logic Design
CDNS - double leaderboard script

Logic Design

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    verilog .v lib vs synopsis .lib

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    1 replies • 14711 views
  • Discussion

    few ques ..

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    1 replies • 12799 views
  • Discussion

    Conformal struggles to resolve abort points (due to complex logic)

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    3 replies • 17939 views
  • Discussion

    How do you find the driving cell?

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    4 replies • 14855 views
  • Discussion

    flat netlist

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    4 replies • 16437 views
  • Discussion

    report on FFs, Latchs

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    1 replies • 12981 views
  • Discussion

    poor performance of LEC compile -parallel

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    1 replies • 742 views
  • Discussion

    CCD: report of certain modules

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    2 replies • 13822 views
  • Discussion

    memory synthesis RTL Compiler commands

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    2 replies • 16291 views
  • Discussion

    E Gates

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    1 replies • 14737 views
  • Discussion

    turn off the unmapped test ports, circuits

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    1 replies • 12940 views
  • Discussion

    TIP OF THE MONTH: How can I compare unreachable logic? Conformal LEC doesn't map nor compare it.

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    2 replies • 5751 views
  • Discussion

    retime failed with error msg "Failed on find_unique_design"

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    7 replies • 8868 views
  • Discussion

    Need to come up to speed on RTL Compiler

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    4 replies • 13666 views
  • Discussion

    Query Post Synthesis vs. Post PAR verification using Conformal

    Category: Logic Design

    By archive archive

    •

    updated over 17 years ago by archive

    4 replies • 14028 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information