Logic Design

Latest Posts

Discussion

verilog .v lib vs synopsis .lib

Category: Logic Design

By archive

$usertype
•
updated over 17 years ago by archive

1 replies • 15587 views
Discussion

few ques ..

Category: Logic Design

By archive

$usertype
•
updated over 17 years ago by archive

1 replies • 13582 views
Discussion

Conformal struggles to resolve abort points (due to complex logic)

Category: Logic Design

By archive

$usertype
•
updated over 17 years ago by archive

3 replies • 19244 views
Discussion

How do you find the driving cell?

Category: Logic Design

By archive

$usertype
•
updated over 17 years ago by archive

4 replies • 15892 views
Discussion

flat netlist

Category: Logic Design

By archive

$usertype
•
updated over 17 years ago by archive

4 replies • 17641 views
Discussion

report on FFs, Latchs

Category: Logic Design

By archive

$usertype
•
updated over 17 years ago by archive

1 replies • 13703 views
Discussion

poor performance of LEC compile -parallel

Category: Logic Design

By archive

$usertype
•
updated over 18 years ago by archive

1 replies • 907 views
Discussion

CCD: report of certain modules

Category: Logic Design

By archive

$usertype
•
updated over 18 years ago by archive

2 replies • 14772 views
Discussion

memory synthesis RTL Compiler commands

Category: Logic Design

By archive

$usertype
•
updated over 18 years ago by archive

2 replies • 17530 views
Discussion

E Gates

Category: Logic Design

By archive

$usertype
•
updated over 18 years ago by archive

1 replies • 15667 views
Discussion

turn off the unmapped test ports, circuits

Category: Logic Design

By archive

$usertype
•
updated over 18 years ago by archive

1 replies • 13733 views
Discussion

TIP OF THE MONTH: How can I compare unreachable logic? Conformal LEC doesn't map nor compare it.

Category: Logic Design

By archive

$usertype
•
updated over 18 years ago by archive

2 replies • 6615 views
Discussion

retime failed with error msg "Failed on find_unique_design"

Category: Logic Design

By archive

$usertype
•
updated over 18 years ago by archive

7 replies • 9437 views
Discussion

Need to come up to speed on RTL Compiler

Category: Logic Design

By archive

$usertype
•
updated over 18 years ago by archive

4 replies • 14614 views
Discussion

Query Post Synthesis vs. Post PAR verification using Conformal

Category: Logic Design

By archive

$usertype
•
updated over 18 years ago by archive

4 replies • 15010 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.