• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Logic Design
CDNS - double leaderboard script

Logic Design

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    simulation of digital circuits

    Category: Logic Design

    By archive archive

    •

    updated over 18 years ago by archive

    1 replies • 13232 views
  • Discussion

    libraries in RTL compiler..

    Category: Logic Design

    By archive archive

    •

    updated over 18 years ago by archive

    1 replies • 13183 views
  • Discussion

    synthesis System Verilog design

    Category: Logic Design

    By archive archive

    •

    updated over 18 years ago by archive

    6 replies • 18900 views
  • Discussion

    Delay values in SDF file

    Category: Logic Design

    By archive archive

    •

    started over 18 years ago

    0 replies • 13758 views
  • Discussion

    TIP OF THE MONTH: gate to gate EC, with different synthesis engines

    Category: Logic Design

    By archive archive

    •

    started over 18 years ago

    0 replies • 12670 views
  • Discussion

    Exit Error in LEC batch mode

    Category: Logic Design

    By archive archive

    •

    updated over 18 years ago by archive

    4 replies • 15025 views
  • Discussion

    The Value of SAT-Solvers in FV

    Category: Logic Design

    By archive archive

    •

    updated over 18 years ago by archive

    1 replies • 13502 views
  • Discussion

    problem with read module

    Category: Logic Design

    By archive archive

    •

    updated over 18 years ago by archive

    1 replies • 13556 views
  • Discussion

    New to RTL Compiler

    Category: Logic Design

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 13428 views
  • Discussion

    How to tell conformal to ignore a module

    Category: Logic Design

    By archive archive

    •

    updated over 18 years ago by archive

    1 replies • 15043 views
  • Discussion

    TIP OF THE MONTH: Black Boxes

    Category: Logic Design

    By archive archive

    •

    started over 18 years ago

    0 replies • 17448 views
  • Discussion

    report flop with constant input

    Category: Logic Design

    By archive archive

    •

    updated over 18 years ago by archive

    1 replies • 13046 views
  • Discussion

    TIP OF THE MONTH: Beware Incomplete Libraries

    Category: Logic Design

    By archive archive

    •

    started over 18 years ago

    0 replies • 12643 views
  • Discussion

    floating input/net and unload ouput

    Category: Logic Design

    By archive archive

    •

    updated over 18 years ago by archive

    1 replies • 721 views
  • Discussion

    floating input/net and unload ouput

    Category: Logic Design

    By archive archive

    •

    started over 18 years ago

    0 replies • 807 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information