Logic Design

Latest Posts

Discussion

Should I bother about the PLL delay?

Category: Logic Design

By gops
•
updated over 13 years ago by grasshopper

2 replies • 13652 views
Discussion

RTL Compiler tutorial

Category: Logic Design

By ubbala
•
updated over 13 years ago by grasshopper

1 replies • 13222 views
Discussion

How to Simulate 64-bit VHDL Code in Cadence?

Category: Logic Design

By shahein
•
started over 13 years ago

0 replies • 12927 views
Discussion

LEC report additional FF

Category: Logic Design

By theodoredj
•
updated over 13 years ago by affaqq

7 replies • 18263 views
Discussion

LEC and Designware components

Category: Logic Design

By jlang
•
updated over 13 years ago by affaqq

1 replies • 13735 views
Discussion

how to map a particular library cell to a component

Category: Logic Design

By gops
•
updated over 13 years ago by renobreint

1 replies • 13417 views
Discussion

CDC Functional Checks taking too much time.

Category: Logic Design

By arunvaidya
•
updated over 13 years ago by arunvaidya

3 replies • 14014 views
Discussion

RTL Compiler: DFT Checks and non controllable/observable I/O

Category: Logic Design

By moogyd
•
updated over 13 years ago by moogyd

6 replies • 4018 views
Discussion

Standard Cell Library Design

Category: Logic Design

By pmuppala
•
updated over 13 years ago by gentle

1 replies • 13703 views
Discussion

dsn-files

Category: Logic Design

By wschira
•
started over 13 years ago

0 replies • 13165 views
Discussion

.so cell import ?

Category: Logic Design

By DavidRo
•
started over 13 years ago

0 replies • 12599 views
Discussion

RC-compiler Error create isolation rule and retention rule failed.....

Category: Logic Design

By yasir khan
•
started over 13 years ago

0 replies • 12854 views
Discussion

CPF_Read Issue

Category: Logic Design

By affaqq
•
updated over 13 years ago by tstark

2 replies • 13357 views
Discussion

clock tree design

Category: Logic Design

By cupidsd
•
started over 13 years ago

0 replies • 12763 views
Discussion

How to see power trace

Category: Logic Design

By ganeshK2012
•
started over 13 years ago

0 replies • 13033 views

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