Mixed-Signal Design

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Discussion

Power supplies of standard cells

Category: Mixed-Signal Design

By KhanAmir

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updated over 2 years ago by KhanAmir

8 replies • 10970 views
Discussion

ocean script if statement not workiing

Category: Mixed-Signal Design

By NewScreenName

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updated over 2 years ago by ShawnLogan

11 replies • 12257 views
Discussion

How to use calcVal for local sweep within the same test?

Category: Mixed-Signal Design

By NewScreenName

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started over 2 years ago

0 replies • 7576 views
Discussion

Hierarchy dump into a file

Category: Mixed-Signal Design

By RaghavendraN

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updated over 2 years ago by Saloni Chhabra

5 replies • 9539 views
Discussion

SKILL script for instance extraction

Category: Mixed-Signal Design

By RaghavendraN

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updated over 2 years ago by RaghavendraN

6 replies • 8910 views
Discussion

No XPS option in ADE

Category: Mixed-Signal Design

By sktf

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updated over 2 years ago by sktf

4 replies • 8850 views
Discussion

I am doing Beh Vs Schematic

Category: Mixed-Signal Design

By sharifsharif

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updated over 2 years ago by Andrew Beckett

4 replies • 8482 views
Discussion

Virtuoso visualization and analysis wiondow does not update in tran analysis

Category: Mixed-Signal Design

By NewScreenName

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updated over 2 years ago by ShawnLogan

3 replies • 8781 views
Discussion

ADE Assembler spec extracted from tran simulation will give error

Category: Mixed-Signal Design

By NewScreenName

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updated over 3 years ago by NewScreenName

2 replies • 8357 views
Discussion

PSS/Pnoise for Correlated Double Samling

Category: Mixed-Signal Design

By Ashwin Rebello

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updated over 3 years ago by Ashwin Rebello

4 replies • 3774 views
Discussion

define different errpreset for different cells in a tran simulation

Category: Mixed-Signal Design

By NewScreenName

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updated over 3 years ago by Andrew Beckett

4 replies • 9598 views
Discussion

data preserving termination of batch run spectre / ADE XL

Category: Mixed-Signal Design

By MinersLamp

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started over 3 years ago

0 replies • 7259 views
Discussion

SystemVerilog AMS simulation (ADE) xmelab ERROR, TYCMPAT: port or terminal connection type check failed on instance (expecting datatype compatible with 'packed array' but found 'unpacked array[0:1] of packed array [3:0] of logic' instead)

Category: Mixed-Signal Design

By ADJK

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updated over 3 years ago by Andrew Beckett

5 replies • 5205 views
Discussion

Verilog-ams generate-for loop with schematic reference

Category: Mixed-Signal Design

By SimbaG

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updated over 3 years ago by SimbaG

1 replies • 9338 views
Discussion

dynamic selection totally freezes layout xl when there are many connectivity warnings

Category: Mixed-Signal Design

By tdtg

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updated over 3 years ago by tdtg

2 replies • 8229 views

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