Mixed-Signal Design

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Discussion

PSS/Pnoise for Correlated Double Samling

Category: Mixed-Signal Design

By Ashwin Rebello
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updated over 2 years ago by Ashwin Rebello

4 replies • 3181 views
Discussion

define different errpreset for different cells in a tran simulation

Category: Mixed-Signal Design

By NewScreenName
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updated over 2 years ago by Andrew Beckett

4 replies • 8573 views
Discussion

data preserving termination of batch run spectre / ADE XL

Category: Mixed-Signal Design

By MinersLamp
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started over 2 years ago

0 replies • 6556 views
Discussion

SystemVerilog AMS simulation (ADE) xmelab ERROR, TYCMPAT: port or terminal connection type check failed on instance (expecting datatype compatible with 'packed array' but found 'unpacked array[0:1] of packed array [3:0] of logic' instead)

Category: Mixed-Signal Design

By ADJK
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updated over 2 years ago by Andrew Beckett

5 replies • 4641 views
Discussion

Verilog-ams generate-for loop with schematic reference

Category: Mixed-Signal Design

By SimbaG
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updated over 2 years ago by SimbaG

1 replies • 8366 views
Discussion

dynamic selection totally freezes layout xl when there are many connectivity warnings

Category: Mixed-Signal Design

By tdtg
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updated over 2 years ago by tdtg

2 replies • 7353 views
Discussion

runams cannot handle environment variables in cds.lib?

Category: Mixed-Signal Design

By zdu89
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updated over 2 years ago by Andrew Beckett

4 replies • 9382 views
Discussion

connectRules for multiple power domain

Category: Mixed-Signal Design

By DavidLou
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updated over 2 years ago by DavidLou

2 replies • 7777 views
Discussion

usage of busset element

Category: Mixed-Signal Design

By paulinho
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updated over 2 years ago by paulinho

1 replies • 8739 views
Discussion

Monte Carlo simulations and returns suspicious results - error in the setup of results?

Category: Mixed-Signal Design

By NewScreenName
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started over 2 years ago

0 replies • 679 views
Discussion

Combine design variables in ADE assembler

Category: Mixed-Signal Design

By NewScreenName
•
updated over 2 years ago by NewScreenName

7 replies • 10316 views
Discussion

Failed to import verilog files

Category: Mixed-Signal Design

By Yongqi Hu
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updated over 2 years ago by Yongqi Hu

6 replies • 11264 views
Discussion

save current data

Category: Mixed-Signal Design

By feixiangzhf
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updated over 2 years ago by Andrew Beckett

1 replies • 7368 views
Discussion

Is that possible to write an external function and call it in Virtuoso Verilog-A through VPI

Category: Mixed-Signal Design

By HiddenOnee
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updated over 2 years ago by HiddenOnee

2 replies • 8353 views
Discussion

xrun simulation elaborates systemverilog real as binary

Category: Mixed-Signal Design

By JayBee
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updated over 2 years ago by JayBee

1 replies • 8655 views

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