Mixed-Signal Design

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Discussion

How to do multi-voltage domain simulation

Category: Mixed-Signal Design

By wangyunxin

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updated over 1 year ago by MarcelAhmedzai

1 replies • 6026 views
Discussion

Changing effective CDF parameters using skill code

Category: Mixed-Signal Design

By Me Daniel

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started over 1 year ago

0 replies • 6649 views
Discussion

Montecarlo variation from file in AMS simulator

Category: Mixed-Signal Design

By NewScreenName

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updated over 1 year ago by Andrew Beckett

1 replies • 5707 views
Discussion

Measuring short circuit current (Shoot-through Current)

Category: Mixed-Signal Design

By Hagar Hendy

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updated over 1 year ago by Andrew Beckett

1 replies • 5615 views
Discussion

How to see the analog voltage of the output signal of the digital module in AMS simulation

Category: Mixed-Signal Design

By wangyunxin

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updated over 1 year ago by Andrew Beckett

1 replies • 5938 views
Discussion

VerilogA blind to DC sweep analysis

Category: Mixed-Signal Design

By NewScreenName

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updated over 1 year ago by Andrew Beckett

11 replies • 9805 views
Discussion

PLL Verification RAK - Total Phase Noise

Category: Mixed-Signal Design

By JoJakNap

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updated over 1 year ago by Andrew Beckett

14 replies • 9904 views
Discussion

AMS simulation IE settings

Category: Mixed-Signal Design

By paulinho

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updated over 2 years ago by paulinho

5 replies • 10264 views
Discussion

Error while running AMS simulations

Category: Mixed-Signal Design

By Ann02

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updated over 2 years ago by Andrew Beckett

3 replies • 7077 views
Discussion

AMS simulation error with bsim bulk model

Category: Mixed-Signal Design

By andreschen

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updated over 2 years ago by Andrew Beckett

1 replies • 5807 views
Discussion

How to set a parameter in a Verilog module as a variable, and send it to the ADE Explorer to scan its different values in simulation?

Category: Mixed-Signal Design

By wangyunxin

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updated over 2 years ago by Andrew Beckett

6 replies • 9529 views
Discussion

fixed-point number in simvision

Category: Mixed-Signal Design

By wangyunxin

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updated over 2 years ago by Andrew Beckett

1 replies • 5848 views
Discussion

SOA checks across multiple PVT runs

Category: Mixed-Signal Design

By NewScreenName

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updated over 2 years ago by ShawnLogan

5 replies • 8888 views
Discussion

Dinamycally changing accuracy of simulator during runtime

Category: Mixed-Signal Design

By NewScreenName

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updated over 2 years ago by NewScreenName

3 replies • 6869 views
Discussion

how to see value of Verilog variable in ams batch mode simulation?

Category: Mixed-Signal Design

By wangyunxin

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updated over 2 years ago by tpylant

1 replies • 9016 views

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