Mixed-Signal Design

Latest Posts

Discussion

define different but related parameters in array of stimuli to ADE

Category: Mixed-Signal Design

By CSCNalu
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updated over 6 years ago by CSCNalu

2 replies • 13921 views
Discussion

Active Mixer Conversion Gain Calculation Issue with the Ports

Category: Mixed-Signal Design

By Mehdi Nasr
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updated over 6 years ago by Andrew Beckett

3 replies • 15245 views
Discussion

SAR ADC Output to MATLAB

Category: Mixed-Signal Design

By growingmind
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updated over 6 years ago by Andrew Beckett

1 replies • 14349 views
Discussion

Overdrive Voltage of a Transistor in Cadence Virtuoso/Spectre

Category: Mixed-Signal Design

By growingmind
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updated over 6 years ago by Andrew Beckett

5 replies • 10149 views
Discussion

Plotting Ids vs Vgs in Cadence of a transistor - Want Y Axis to be Square Root of IDS

Category: Mixed-Signal Design

By growingmind
•
updated over 6 years ago by Andrew Beckett

1 replies • 3935 views
Discussion

Problems with AHDL Block Rand Bit Stream in Cadence Virtuoso using Spectre RF

Category: Mixed-Signal Design

By growingmind
•
updated over 6 years ago by Andrew Beckett

1 replies • 13614 views
Discussion

Want to add Noise in VPWL source along with ECG signal

Category: Mixed-Signal Design

By mohammadalizia
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updated over 6 years ago by Andrew Beckett

4 replies • 15199 views
Discussion

Unable to edit a cellview in a RAK

Category: Mixed-Signal Design

By mhkvy4
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updated over 6 years ago by mhkvy4

10 replies • 17858 views
Discussion

Differences in resistor noise Verilog-A model

Category: Mixed-Signal Design

By JimmyLin
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updated over 6 years ago by Andrew Beckett

5 replies • 17166 views
Discussion

verilogA simulation of 2nd order Sigma-Delta modulator

Category: Mixed-Signal Design

By VivekNITg
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updated over 6 years ago by Andrew Beckett

4 replies • 18559 views
Discussion

OCEAN Tutorial

Category: Mixed-Signal Design

By growingmind
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updated over 6 years ago by Andrew Beckett

5 replies • 20143 views
Discussion

Spectre simulation with schematic in Verilog-A

Category: Mixed-Signal Design

By JimmyLin
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updated over 6 years ago by JimmyLin

4 replies • 17315 views
Discussion

Detecting floating node in schematic in Verilog-A code

Category: Mixed-Signal Design

By vasug7
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updated over 6 years ago by Andrew Beckett

3 replies • 16028 views
Discussion

How to make schematic CDF parameter become integer in AMS?

Category: Mixed-Signal Design

By drdanmc
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updated over 7 years ago by drdanmc

2 replies • 15992 views
Discussion

DC offset

Category: Mixed-Signal Design

By Charanraj Mohan
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updated over 7 years ago by Frank Wiedmann

1 replies • 18726 views

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