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Mixed-Signal Design

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  • Discussion

    SysVerilog bidirectional port with wreal nettype from cds_rnm_pkg

    Category: Mixed-Signal Design

    By HoWei

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    updated over 2 years ago by HoWei

    4 replies • 11204 views
  • Discussion

    calcVal outcome depends on enabled test (although no calcVal is referring to such test)

    Category: Mixed-Signal Design

    By NewScreenName

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    updated over 2 years ago by delgsy

    16 replies • 13537 views
  • Discussion

    Changing parameters during AMS simulation

    Category: Mixed-Signal Design

    By AFNielsen

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    started over 2 years ago

    0 replies • 6669 views
  • Discussion

    print noise summary from ADE assembler does not work as explained in cadence support website

    Category: Mixed-Signal Design

    By NewScreenName

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    updated over 2 years ago by NewScreenName

    7 replies • 11506 views
  • Discussion

    applying a transfer function to the phase noise plot

    Category: Mixed-Signal Design

    By matcha

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    updated over 2 years ago by ShawnLogan

    3 replies • 8717 views
  • Discussion

    Are there predefined macros in XCELIUM (e.g. to be used with 'ifdef )

    Category: Mixed-Signal Design

    By HoWei

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    started over 2 years ago

    0 replies • 1612 views
  • Discussion

    PAC simulation results

    Category: Mixed-Signal Design

    By mxm14

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    updated over 2 years ago by mxm14

    3 replies • 9494 views
  • Discussion

    SystemVerilog nettype and resolution function in Virtuoso schematic hierarchy

    Category: Mixed-Signal Design

    By HoWei

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    updated over 2 years ago by VatcheSouvalian

    5 replies • 12236 views
  • Discussion

    Drive/monitor EEnet using virtual interface

    Category: Mixed-Signal Design

    By jshaler

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    updated over 2 years ago by jshaler

    2 replies • 1366 views
  • Discussion

    Pac Simulation Sideband Sweep Parameter

    Category: Mixed-Signal Design

    By mxm14

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    updated over 2 years ago by Andrew Beckett

    1 replies • 7156 views
  • Discussion

    RMS value of transient sub-interval

    Category: Mixed-Signal Design

    By Daniel Stracke

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    updated over 2 years ago by Daniel Stracke

    2 replies • 7762 views
  • Discussion

    write a verilog-A for inverter

    Category: Mixed-Signal Design

    By Hagar Hendy

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    updated over 2 years ago by Hagar Hendy

    2 replies • 13252 views
  • Discussion

    read a file .csv and .mat with verilog-A

    Category: Mixed-Signal Design

    By Hagar Hendy

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    updated over 2 years ago by Andrew Beckett

    13 replies • 14442 views
  • Discussion

    PLL PSS simulation in spectre

    Category: Mixed-Signal Design

    By RaghavendraN

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    updated over 2 years ago by ShawnLogan

    1 replies • 9036 views
  • Discussion

    Importing the waveform (.tran) file in any format in another test bench to run the simulation?

    Category: Mixed-Signal Design

    By mnmz

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    updated over 2 years ago by ShawnLogan

    1 replies • 8407 views
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