Mixed-Signal Design

Latest Posts

Discussion

Differences between Verilog, Verilog-A, Verilog-AMS and SystemVerilog

Category: Mixed-Signal Design

By HoWei
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updated over 2 years ago by HoWei

2 replies • 24221 views
Discussion

Error in Running the simulation

Category: Mixed-Signal Design

By Upendra Ch
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updated over 2 years ago by ShawnLogan

1 replies • 6840 views
Discussion

Design of CMOS switch

Category: Mixed-Signal Design

By Shankaranarayana
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updated over 2 years ago by ShawnLogan

1 replies • 6603 views
Discussion

How to find the period of $urandom generator of Xcelium

Category: Mixed-Signal Design

By nustisb1
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updated over 2 years ago by Andrew Beckett

3 replies • 6708 views
Discussion

Is it possible to delete one or two data points from a 1000 point Monte Carlo run simulation.

Category: Mixed-Signal Design

By mukulmishra5
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updated over 2 years ago by Andrew Beckett

1 replies • 7572 views
Discussion

monte Carlo simulations for an analog circuit

Category: Mixed-Signal Design

By randhiru
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updated over 2 years ago by Andrew Beckett

2 replies • 7256 views
Discussion

SysVerilog bidirectional port with wreal nettype from cds_rnm_pkg

Category: Mixed-Signal Design

By HoWei
•
updated over 2 years ago by HoWei

4 replies • 9898 views
Discussion

calcVal outcome depends on enabled test (although no calcVal is referring to such test)

Category: Mixed-Signal Design

By NewScreenName
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updated over 2 years ago by delgsy

16 replies • 11864 views
Discussion

Changing parameters during AMS simulation

Category: Mixed-Signal Design

By AFNielsen
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started over 2 years ago

0 replies • 5963 views
Discussion

print noise summary from ADE assembler does not work as explained in cadence support website

Category: Mixed-Signal Design

By NewScreenName
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updated over 2 years ago by NewScreenName

7 replies • 10112 views
Discussion

applying a transfer function to the phase noise plot

Category: Mixed-Signal Design

By matcha
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updated over 2 years ago by ShawnLogan

3 replies • 7699 views
Discussion

Are there predefined macros in XCELIUM (e.g. to be used with 'ifdef )

Category: Mixed-Signal Design

By HoWei
•
started over 2 years ago

0 replies • 1407 views
Discussion

PAC simulation results

Category: Mixed-Signal Design

By mxm14
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updated over 2 years ago by mxm14

3 replies • 8335 views
Discussion

SystemVerilog nettype and resolution function in Virtuoso schematic hierarchy

Category: Mixed-Signal Design

By HoWei
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updated over 2 years ago by VatcheSouvalian

5 replies • 10646 views
Discussion

Drive/monitor EEnet using virtual interface

Category: Mixed-Signal Design

By jshaler
•
updated over 2 years ago by jshaler

2 replies • 1171 views

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