• Discussion

  error in assura rcx (parasitic extraction) Locked

  13966 views
  1 reply
  Latest over 13 years ago
  by Quek
• Discussion

  Nodeset for subcircuit Locked

  16504 views
  2 replies
  Latest over 13 years ago
  by Andrew Beckett
• Discussion

  How to reach "analog" signals at higher/lower hierarchy using VerilogAms? Locked

  732 views
  1 reply
  Latest over 13 years ago
  by yayla
• Discussion

  Assura LVS - number of edges of first layer butting/coincident with the second layer Locked

  846 views
  1 reply
  Latest over 13 years ago
  by Quek
• Discussion

  Custom Cellview: Callback some skill procedure when double click in Library Manager view list Locked

  14439 views
  2 replies
  Latest over 13 years ago
  by TamalDas
• Discussion

  How to store components location

  13551 views
  2 replies
  Latest over 13 years ago
  by GIL2004XP
• Discussion

  axlShell() and select function

  13946 views
  1 reply
  Latest over 13 years ago
  by GIL2004XP
• Discussion

  using axlDMFileBrowse to select files

  12739 views
  0 replies
  Started over 13 years ago
  by GIL2004XP
• Discussion

  overlay plotting problem Locked

  14714 views
  4 replies
  Latest over 13 years ago
  by MatthewM
• Discussion

  Library scaling Locked

  14196 views
  1 reply
  Latest over 13 years ago
  by mamsadegh
• Discussion

  analog-mixed signal simulation with verilog-a vhdl and circuit components Locked

  16241 views
  4 replies
  Latest over 13 years ago
  by Zitty
• Discussion

  mmsim61 Locked

  13430 views
  1 reply
  Latest over 13 years ago
  by Andrew Beckett
• Discussion

  Running brd2odb using command line with suppress shape option

  14050 views
  2 replies
  Latest over 13 years ago
  by GIL2004XP
• Discussion

  How to Find content of Bonding Box. Locked

  13948 views
  2 replies
  Latest over 13 years ago
  by ShrikantTI
• Discussion

  Differential pairs for DVI/HDMI signals Locked

  3262 views
  2 replies
  Latest over 13 years ago
  by redwire