• Discussion

  RC TNS optimization is not enough Locked

  14060 views
  1 reply
  Latest over 16 years ago
  by archive
• Discussion

  VHDL Verilog Co-simulation in NCVerilog Locked

  13938 views
  0 replies
  Started over 16 years ago
  by archive
• Discussion

  how to get top_cell instances cellName i.e including depth Locked

  13811 views
  1 reply
  Latest over 16 years ago
  by Andrew Beckett
• Discussion

  Orcad Layout 15.7 -SST -file missing in post processing output Locked

  3718 views
  6 replies
  Latest over 16 years ago
  by netmo
• Discussion

  Change text height

  13539 views
  2 replies
  Latest over 16 years ago
  by oldmouldy
• Discussion

  Allegro Artwork Filename Length Locked

  14668 views
  5 replies
  Latest over 16 years ago
  by dschaefer
• Discussion

  DRC Error "ERROR: [DRC0025] The comment graphic is not a single dashed line" Locked

  4471 views
  2 replies
  Latest over 16 years ago
  by AnandS
• Discussion

  Capture slow down issue in 16.2 Locked

  13681 views
  3 replies
  Latest over 16 years ago
  by EvanShultz
• Discussion

  ERROR: [DRC0016] User properties exist on an object that is not a part instance Locked

  14869 views
  1 reply
  Latest over 16 years ago
  by oldmouldy
• Discussion

  How to set offset of a shape in a padstack in Allegro? Locked

  14440 views
  1 reply
  Latest over 16 years ago
  by Rik Lee
• Discussion

  How to check if all component pins are connected in ConceptHDL. Locked

  13079 views
  1 reply
  Latest over 16 years ago
  by Jerry GenPart
• Discussion

  Welcome to the Allegro PCB SI Forum Locked

  13178 views
  1 reply
  Latest over 16 years ago
  by archive
• Discussion

  Setting up Buses Locked

  13773 views
  1 reply
  Latest over 16 years ago
  by Rik Lee
• Discussion

  Dynamic shape going out of date when editing constraint Locked

  13185 views
  2 replies
  Latest over 16 years ago
  by NormK2
• Discussion

  EXPORT COMPONENTS FROM ALLEGRO TO PCAD Locked

  13312 views
  1 reply
  Latest over 16 years ago
  by Rik Lee