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Forum - Thread List
  • Discussion

    how to add padstacks to a package design? Locked

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    Latest over 16 years ago
    by Rik Lee
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    Net list error Locked

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    Latest over 16 years ago
    by oldmouldy
  • Discussion

    display packet information 'defaultPacket' not found Locked

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    1 reply
    Latest over 16 years ago
    by dmay
  • Discussion

    RC doesn't use up all available memory and crashes Locked

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    2 replies
    Latest over 16 years ago
    by naderi
  • Discussion

    how to export gds file using skill Locked

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    1 reply
    Latest over 16 years ago
    by Andrew Beckett
  • Discussion

    Adding Pin numbers to Resisitor and Caps Locked

    12834 views
    1 reply
    Latest over 16 years ago
    by oldmouldy
  • Discussion

    sp simulation with old dc operating point Locked

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    2 replies
    Latest over 16 years ago
    by Frank Wiedmann
  • Discussion

    Issue with subckt view Locked

    15018 views
    3 replies
    Latest over 16 years ago
    by Jon CY
  • Discussion

    Extremely slow OrCAD 16.0 Locked

    17207 views
    2 replies
    Latest over 16 years ago
    by trieste
  • Discussion

    Can the drill legend board markers be turned off on the Drill Legend layer? Locked

    13102 views
    1 reply
    Latest over 16 years ago
    by redwire
  • Discussion

    How to get width of a polygon? Locked

    14985 views
    2 replies
    Latest over 16 years ago
    by ToMWUT
  • Discussion

    RC TNS optimization is not enough Locked

    14055 views
    1 reply
    Latest over 16 years ago
    by archive
  • Discussion

    VHDL Verilog Co-simulation in NCVerilog Locked

    13932 views
    0 replies
    Started over 16 years ago
    by archive
  • Discussion

    how to get top_cell instances cellName i.e including depth Locked

    13806 views
    1 reply
    Latest over 16 years ago
    by Andrew Beckett
  • Discussion

    Orcad Layout 15.7 -SST -file missing in post processing output Locked

    3707 views
    6 replies
    Latest over 16 years ago
    by netmo
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