• Discussion

  Adding Spiral Inductors to PDK Locked

  6604 views
  1 reply
  Latest over 2 years ago
  by ShawnLogan
• Discussion

  skill code to get all the pins in a schematic and add noCon or a inverter to it Locked

  6065 views
  0 replies
  Started over 2 years ago
  by jk1379
• Discussion

  pcreCompile and use of OR in search pattern Locked

  8740 views
  7 replies
  Latest over 2 years ago
  by FuadBadrieh
• Discussion

  Different ways to achieve sequential reference designators (RefDes)

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  0 replies
  Started over 2 years ago
  by Krishnadas
• Discussion

  wildcards with "ic" statement Locked

  3795 views
  8 replies
  Latest over 2 years ago
  by Andrew Beckett
• Discussion

  when i do ams sim, i want to save a portion of the simulation data? Locked

  7451 views
  1 reply
  Latest over 2 years ago
  by Andrew Beckett
• Answered

  [Allegro Free Physical Viewer] Issue - Error : Design revision 1024.x is newer than current program +1

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  3 replies
  Latest over 2 years ago
  by John T
• Discussion

  hi*Layout expanding string/button fields in the gui Locked

  3084 views
  5 replies
  Latest over 2 years ago
  by Andrew Beckett
• Answered

  Abnormal text size for UI 0

  9482 views
  8 replies
  Latest over 2 years ago
  by Bao Nguyen 0412
• Discussion

  [Spectre netlist] How to contain/have all the subckt definitions of sub-blocks and devices included in a top level cell inside the top level subckt definition ? Locked

  1815 views
  2 replies
  Latest over 2 years ago
  by MFahmy
• Discussion

  How to use the same Plotting Template from different Maestro file? Locked

  5775 views
  0 replies
  Started over 2 years ago
  by delgsy
• Discussion

  Virtuoso Layout GXL Locked

  6625 views
  1 reply
  Latest over 2 years ago
  by RobMan
• Discussion

  Xtensa TIE documentation Locked

  6881 views
  0 replies
  Started over 2 years ago
  by ciapata
• Discussion

  How to Short Two Nets or Two Nodes on the Board in Cadence System Analysis Sigrity PowerSI tool?

  5486 views
  1 reply
  Latest over 2 years ago
  by SimTech
• Answered

  VIA to VIA spacing isn't true in allegro cadence. +1

  2799 views
  3 replies
  Latest over 2 years ago
  by mcatramb91