• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Not Answered

    PSPICE for TI - TPS2662x - Fixed OVP 0

    114 views
    1 reply
    Latest 6 days ago
    by AyushD
  • Not Answered

    Query on Line Segments connecting to Nets 0

    371 views
    5 replies
    Latest 6 days ago
    by excellon1
  • Discussion

    DC convergence problem with Basic ring amplifier

    198 views
    2 replies
    Latest 6 days ago
    by SC202503236954
  • Discussion

    Sorting variables by name alphanumerically in Virtuoso ADE Assembler / maestro

    169 views
    1 reply
    Latest 6 days ago
    by Andrew Beckett
  • Discussion

    sweeping transistor number of fingers in a simulation

    638 views
    2 replies
    Latest 6 days ago
    by TommasoF
  • Discussion

    Need a script to remove extra metal overhang after vias which we generally chop and delete manually

    1148 views
    1 reply
    Latest 7 days ago
    by rajeshcad
  • Discussion

    Ring oscillator separation gate delay and interconnect delay

    119 views
    0 replies
    Started 7 days ago
    by SL202509028216
  • Not Answered

    Using Presto every day is a real struggle with all the bugs and crashes, etc. Anyone else using it 100% of the time? Is the other pcb editor as buggy? 0

    807 views
    5 replies
    Latest 7 days ago
    by KK202508144032
  • Discussion

    Meet the Champion of the Month: August 2025

    82 views
    0 replies
    Started 7 days ago
    by MohitS
  • Not Answered

    Orcad capture 22 title block auto population 0

    224 views
    2 replies
    Latest 8 days ago
    by MR20250829531
  • Discussion

    xrun: *F,SROOTE: Cannot find the Spectre installation

    426 views
    3 replies
    Latest 8 days ago
    by Andrew Beckett
  • Discussion

    use DC sweep variable to set another variable

    403 views
    2 replies
    Latest 8 days ago
    by Darrell L
  • Discussion

    Attach load to a pin for AMS verification

    126 views
    0 replies
    Started 8 days ago
    by PedroC
  • Discussion

    Code coverage syntax for scripting tcl exclusion file

    233 views
    1 reply
    Latest 8 days ago
    by StephenH
  • Discussion

    automate cadence design to avoid time consuming steps for simulation using python subprocess module.

    177 views
    0 replies
    Started 8 days ago
    by AP202507218251
<>

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information