• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    Do you know convergence skill in tran(dcop)? Locked

    1486 views
    3 replies
    Latest over 4 years ago
    by ichiro
  • Discussion

    Default settings for cell mapping - Genus Synthesis (Legacy) Locked

    6542 views
    0 replies
    Started over 4 years ago
    by iamKarthikBK
  • Discussion

    Xcelium notation worklib:cell:view Locked

    3965 views
    0 replies
    Started over 4 years ago
    by Yakir
  • Discussion

    Get defines value from Xcelium simulation Locked

    14772 views
    0 replies
    Started over 4 years ago
    by Yakir
  • Discussion

    Error When Running AMS Simulations with Both VHDL and Verilog in Digital Heirarchy Locked

    12937 views
    3 replies
    Latest over 4 years ago
    by amrao
  • Discussion

    Cadence Liberate CCS Power Characterization Accuracy Locked

    13815 views
    4 replies
    Latest over 4 years ago
    by anurans
  • Discussion

    Shape defined soldermask in component doesn't show in 3D

    1394 views
    2 replies
    Latest over 4 years ago
    by Fredda
  • Discussion

    Allegro crashes when assigning net to via

    12235 views
    4 replies
    Latest over 4 years ago
    by AvengerThanos
  • Discussion

    scaling pin spacing - ideas on imposing a minimum between pins Locked

    1024 views
    0 replies
    Started over 4 years ago
    by aicdesigner
  • Discussion

    Is there leakage current in Analoglib's cap? Locked

    1108 views
    1 reply
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    How to force RTL compiler to use a particular net name Locked

    19767 views
    4 replies
    Latest over 4 years ago
    by Rameen
  • Discussion

    Slow down when opening many results Locked

    13891 views
    4 replies
    Latest over 4 years ago
    by Simon T
  • Discussion

    UNCONNECTED NETS in GENUS NETLIST! Locked

    16703 views
    1 reply
    Latest over 4 years ago
    by Rameen
  • Discussion

    Input referred noise current through pnoise Locked

    19246 views
    4 replies
    Latest over 4 years ago
    by sahand1400
  • Discussion

    Need skill file for net assignment

    10375 views
    3 replies
    Latest over 4 years ago
    by RFinley
<>

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information