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Understandably, EDA industry observer John Cooley had to edit down all the submissions to his annual DAC "Cheesy Must See List".  Unfortunately, the entry for Incisive Enterprise Manager ended up in the wrong spot, and with too short a description to really understand it.  So below is what you want to know about Incisive Enterprise Manager.  Hope to see you in San Diego!

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YOUR COMPANY: Cadence

YOUR TOOL: Incisive…

Understandably, EDA industry observer John Cooley had to edit down all the submissions to his annual DAC "Cheesy Must See List".  Hence, allow us to share the complete text that we submitted for Incisive Enterprise Verifier's Assertion-Driven Simulation capability.  Hope to see you in San Diego!

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YOUR COMPANY: Cadence

YOUR TOOL: Incisive Formal Verifier and Incisive Enterprise Verifier

WHAT TOOL DOES: Formal…

While Assertion-Based Verification (ABV) has been around for many years, ABV has largely been a passive exercise.  For example, assertions can monitor behavior in a simulation environment, model a formal analysis environment with constraints, or provide targets for formal proofs as checks or covers.  This is all very useful and good.  However, assertions are passive objects in these cases.  This means that in simulation you…

In this posting, I continue looking at applications of SKILL++. In particular, I'll also discuss how to create functions that hold onto their state. I'll use these functions to implement multiple-criteria (cascading) sort predicates. I'll look at ways to sort layout pins counter-clockwise around the center point of the design.

 In the previous posting we looked at an implementation of ge…

Talk about stability -- OVM 2.1.1 has had 18 months as the core of Accellera's UVM and accumulated only 13 bugs.  Not too shabby!  With the OVM community preparing to migrate, Cadence and Mentor have posted a bug-fix update -- OVM 2.1.2 -- to OVMWorld to help you get ready to move to the UVM.

As you may have seen in my twitter feed, I've been out talking to customers a lot lately.  Both OVM and VMM users have been…

The Allegro 16.5 release was made available on May 17, 2011!

This release adds additional improvements and efficiencies to your design process.

New technologies in Allegro 16.5 include advanced miniaturization capabilities, integrated power delivery network analysis, DDR3 design-in kit, bolstered co-design featured and flexible team-design enablement to address global designer productivity.

You can read Richard Goering’s…

A new thing that we're seeing with some 45nm libraries is the rule that single-wide filler cells should not be used. At first, this may seem like a difficult thing to ensure in your design flow, but Encounter Digital Implementation system has the ability to handle this. You just have to know the right settings -- and today you'll learn them in five minutes or less.

First, we need to tell the placer that we don…

“You’re only as good as your last product …”

We have been talking about low power simulation and the Common Power Format (CPF) for five or six years now. It’s become popular in most digital designs thanks to a mature methodology and design flow. However, more and more SoC designs are coming up with mixed-signal content. How will low power technologies and formats be used in mixed-signal design?

Being a Marketing guy, one thing that I really enjoy is getting on the road for a big, splashy seminar series. For many EDA companies, that used to be a routine annual event with 30 or 40 locations around the world. We'd split them up and visit perhaps 8 or 10 cities apiece. The pace could be a bit brutal at times, sometimes literally five countries in five days, but seminars provide a great chance to get out of…

If there's one thing that makes navigating a UNIX command line or tool console more efficient, it's tab completion. We've been improving Encounter's support for tab completion over the past few releases, and in 10.1 Encounter's dbGet command received tab completion support for the first time. Have a look at the screencast embedded below -- I think the way it's been implemented is really nice. And smarter than you might…

It's hard to believe there was a time when we didn't even run signal integrity analysis. It wasn't always a necessity at the larger nodes of several years ago, but it's absolutely essential in today's processes. So I'm sure every one of you out there has battled SI violations at some point. Today's tutorial will show you a quick and easy way to reroute some victim nets in EDI and get some of your SI issues under control…

No more having to leave Capture to open a browser to search for a part or a symbol. The Marketplace does all of this for you. You can click right into the Marketplace within OrCAD Capture and go to the…

Every once in a while, I like to do a lightweight blog post linking my work world of functional verification with the real world. Regular readers may recall my series explaining MDV using quotes from classic Hollywood movies. Today I pose a question: if you had assertions available in your everyday life, where would you use them? Yes, it's a nerdy way of thinking but it's not as if I actually go around saying to…

Last week teammate Adam Sherer and I had the honor of representing the Incisive functional verification platform at the annual CDNLive for Europe, the Middle East and Africa (EMEA) in Munich, Germany.  Among our tasks was to deliver the annual verification roadmap update; support numerous techtorials, demos, and papers; and of course meet with customers and partners.  Along the way I couldn't resist taking a few pictures…

Hi, and welcome back to another Five-Minute Tutorial! Yes, I know it's been a while, but like most of you out there, I'm an ASIC designer, and you know how busy work can get. (Blogging is not my day job, but I enjoy doing it when I have some extra time!)

Today's topic is how to set up your clock routing rules in Encounter. This is best done in the .ctstch file, so that your clocks are routed the way you want from…

As consumers we are very familiar with product miniaturization trends. We demand more functionality in smaller sizes that have longer battery life all the time. The electronics market has been delivering to those customer expectations not just in consumer electronics marketplace, but in all market segments.

Allow us to shamelessly promote a free webinar (including a live demo) this Thursday May 12 at 10am-11am Pacific time, entitled "Verification 1-2-3 with Assertion-Driven Simulation".   In a nutshell, in this webinar Solutions Architect Chris Komar and Product Management Director Joe Hupcey III of Team Verify will show a new approach using both formal and dynamic simulation technologies to increase bug detection…

In my last blog, Virtuoso IC 5.1.41 was Good but Virtuoso IC6.1 is Better, I wrote about the improvements in Open Access, SKILL and Virtuoso Schematic Editor in Virtuoso IC 6.1. In this blog, I am going to focus on Virtuoso Analog Design Environment, mainly on Virtuoso Analog Design Environment XL, its design analysis and verification capabilities, and how design teams can take advantage of these features to increase…