Industry Insights Blogs

In 1985, as a relatively new editor at Computer Design magazine, I was asked to go forth and cover a new business called CAE (computer-aided engineering). I knew nothing about it, but I had been writing about design for test, so there seemed to be somewhat of a connection. Little did I know that “CAE” would turn into “EDA” and that I’d write about it for the next 30 years, for Computer Design , EE Times, Cadence, and...

EDA investor and former executive Jim Hogan is optimistic about automotive electronics, but he has some concerns as well. At the recent Design Automation Conference (DAC 2015), he delivered a speech titled “The Looming Quality, Reliability, and Safety Crisis in Automotive Electronics...Why is it and what can we do to avoid it?" Hogan gave the keynote speech for IP Talks!, a series of over 30 half-hour presentations...

Let’s face it – the EDA industry needs new people and new ideas. One of the best places to find both is academia, and a presentation at the Cadence Theater at the recent Design Automation Conference ( DAC 2015 ) described collaboration models that are working today. The presentation was titled “Industry/Academia Engagement Models – From PhD Contests to R&D Collaborations.” It included these speakers, shown from left...

Design and verification standards are critical if we want to get a new generation of Internet of Things (IoT) devices into the market, according to panelists at an Accellera Systems Initiative breakfast at the Design Automation Conference ( DAC 2015 ) June 9. However, IoT devices for different vertical markets pose very different challenges and requirements, making the standards picture extremely complicated. The...

As a leading venture capitalist in the electronics technology, as well as CEO of Cadence, Lip-Bu Tan has unique insights into ongoing changes that will impact EDA providers and users. Tan shared some of those insights in a “fireside chat” with Ed Sperling, editor in chief of Semiconductor Engineering, at the Design Automation Conference ( DAC 2015) on June 9. Topics of this discussion included industry consolidation...

There has been so much hype about the “Internet of Things” (IoT) that it is refreshing to hear about a cutting-edge development project that can bring concrete benefits to millions of people. That project is the ongoing development of the Google Smart Contact Lens, and it was detailed in a keynote speech June 8 at the Design Automation Conference ( DAC 2015 ). The keynote speech was given by Brian Otis (right), a...

First, the good news. The EDA industry will grow from $6.2 billion in 2015 to $9.0 billion in 2019, according to Gary Smith, chief analyst at Gary Smith EDA . Year-to-year growth rates will range from +4% to +11.2%. But in his annual presentation on the eve of the Design Automation Conference (DAC 2015), Smith noted that Wall Street is unimpressed. “The people I talk to want long-term steady growth, no sharp up-turns...

Formal verification is a complex technology that has traditionally required experts or specialized teams who stood apart from the IC design and verification flow. Taking a different approach, a new release of the Cadence JasperGold formal verification platform (June 8, 2015) provides formal techniques that complement simulation, emulation, and debugging in the form of “Apps” or under-the-hood solutions that any design...

One reason for attending the upcoming Design Automation Conference ( DAC 2015 ) is to learn about challenges other engineers have faced, and hear about their solutions. And the best place to do that is the Cadence Theater , located at the Cadence booth (#3515). The Theater will host continuous half-hour customer and partner presentations from 10:00 am Monday, June 8, to 5:30 pm Wednesday June 4. As of this writing...

Physical synthesis has been around in various forms for many years. The basic idea is to bring some awareness of physical layout into synthesis. This week (June 3, 2015) Cadence is rolling out the Genus™ Synthesis Solution , a next-generation RTL synthesis tool that takes physical awareness in some new directions. Here are four important things to know about Genus technology: A massively parallel architecture...

If you’re a system on chip (SoC) designer, you need the latest, most up to date information about semiconductor design IP and verification IP (VIP). And the best place to find that is at IP Talks!, a series of ongoing presentations at the ChipEstimate.com booth (#2433) at the Design Automation Conference 2015 ( DAC 2015 ), taking place June 8-11 in San Francisco, California. Now going into its 9 th year, IP Talks...

It’s been five years since Cadence acquired Denali Software, and that will be the cause for some extra celebration at the Denali Party at this year’s Design Automation Conference (DAC 2015). To help set some context for this milestone, Brian Fuller and I had a recent conversation with Sanjay Srivastava, CEO of Denali until the Cadence acquisition. In this interview, Srivastava talks about the history of Denali, the Cadence...

In mid-2014, Cadence completed its purchase of Jasper Design Automation, and became the overnight leader in the formal verification market. Many Jasper formal verification experts came to work for Cadence, among them Oz Levia, who, as vice president of R&D, leads the new Formal and Automated Verification (FAV) business unit at Cadence. In this interview Levia talks about how formal technologies complement simulation...

According to Lars Reger, CTO of the NXP Semiconductors Automotive Division, “semiconductor development is getting cool again.” In a fast-moving keynote speech at CDNLive EMEA 2015 in Munich, Germany, Reger reviewed a number of “cool” leading-edge technologies that NXP is bringing to the automotive market. Reger took the audience on a whirlwind tour of emerging technologies for car-to-car communications, remote car...

It’s time once again for the biggest annual event for EDA and semiconductor IP developers and users—the 52 nd annual Design Automation Conference (DAC 2015). This year’s conference takes place June 7-11 in San Francisco, California. Cadence is a Platinum Sponsor and is actively participating in exhibits, technology presentations, papers, panels, and luncheon and breakfast events—and, of course, is offering the world...

Will you use FinFET or FD-SOI (fully depleted silicon-on-insulator) technology in your next IC design? At a panel discussion at the recent Electronic Design Process Symposium ( EDPS 2015 ), industry experts debated the advantages and tradeoffs of these technologies for Internet of Things (IoT) and other applications. A three-hour “FD-SOI vs. FinFET” session started with a keynote speech by Tom Dillinger, CAD technology...

If you’re designing an IC today, you have three types of transistors to choose from – traditional bulk planar FETs (down to 20nm), FinFETs (below 20nm), and FD-SOI (fully depleted silicon-on-insulator, 28nm). How can you make the best choice for your design? A session at the recent Electronic Design Process Symposium ( EDPS 2015 ) provided a wealth of information to help you decide. The three-hour “ FD-SOI vs. FinFET...

In the past few years, it has become clear that no single development platform will fulfill all the needs of system-on-chip (SoC) designers and programmers who must do their work before silicon is completed. Today the picture is getting even more complex with “hybrid” platforms that combine the capabilities of existing development platforms, such as virtual prototyping and emulation. At the Electronic Design Process...

Debugging is becoming the biggest bottleneck in the IC functional verification flow, and no wonder—many verification engineering teams are spending at least 50% of their time in debug. Cadence this week (April 28, 2015) is seeking to ease that bottleneck with the Indago™ Debug Platform , which is based on two concepts that are being applied across many industries: root cause analysis and Big Data . Part of the Cadence...

The EDA industry provides impressive tools for block-level verification test generation, but has so far produced limited automation for debugging. As a result, debug is becoming a major bottleneck in IC functional verification. Shlomi Uziel (right), vice president of engineering at the Advanced Verification Solutions Group at Cadence, is among those who believe that a new approach to debug is needed. In this interview...

The 10nm semiconductor process node is no longer in the distant future – it is here today, according to presenters at the recent TSMC 2015 Technology Symposium in San Jose, California. TSMC executives noted that EDA tools have been certified, most of the IP is ready or close to ready, and risk production is expected to begin in the fourth quarter of 2015. The good news is that scaling still works. Due to aggressive...

As the world’s largest pure-play foundry, TSMC pioneers advanced process nodes for leading-edge semiconductor design companies. At the recent TSMC 2015 Technology Symposium in San Jose, however, much of the emphasis was on the “mainstream” part of TSMC’s roadmap, where TSMC introduced two new processes – 16nm FinFET C (16FFC) and 28nm HPC+. 16FFC is a “compact” version of the 16nm FinFET+ (16FF+) process technology...

Monte Carlo statistical simulations are crucial for predicting and improving yields in custom/analog IC design, but run times are becoming unwieldy at advanced process nodes. As described in a recently archived webinar , Cadence and TSMC collaborated to develop a new technique that can provide a performance improvement over statistical simulation using traditional methods. The new method, developed for the TSMC 16nm...

The Design Automation Conference (DAC 2015) program is now live, and perhaps not surprisingly, this year’s program has a strong emphasis on the Internet of Things (IoT). DAC 2015 is thus a great opportunity to learn what’s hype and what’s real about IoT, and what it will take to design the billions of connected devices that industry observers expect to be all around us in just a few years. DAC 2015 runs June 7-11...

Industry “wisdom” once held that analog/mixed-signal designers will stay away from leading-edge process nodes that employ FinFET transistors, but that turned out to be wrong. FinFET processes in fact bring many advantages to analog/mixed-signal designers, but they’ll have to accept a number of changes in the way IC design is done, according to Eric Naviasky (right), fellow in the IP Group at Cadence. In a recently...