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In some designsflows, you need to connect two plane shapes on the same net, but on different layers, together with vias in order to improve connectivity. These “shorting” vias are placed in a regular pattern across the overlapping areas of the shape, in such a way as not to interfere with any routing on layers between the two shapes.

The 16.6 Allegro Package Designer (APD) product now provides a mechanism…

The trend of combining analog and digital circuits on a single chip has been growing for several years. More recently I'm seeing more and more designers improve their productivity by transitioning their designs to Open Access (OA) and taking advantage of the interoperability between Virtuoso and the Encounter Digital Implementation (EDI) System.  Whether you're performing floorplanning in Virtuoso (schematic-driven…

MMSIM 12.1 contains many new features to aid RF designers. Here's a preview of the changes...

Documentation Improvements

The SpectreRF User Guide is being completely rewritten and updated for MMSIM12.1.  Check it out - I'm sure you'll really...

Working with the conventional Specman C language interface has two major disadvantages:

1.       There is a tight dependency between the e code and the C code. The user must include the Specman header file which was generated based on the e code. Every minor change in the e code requires regeneration of the header file.

2.       The C interface doesn't support calling e TCMs (Time Consuming Methods) from C code.

Let's take a look…

The Component Alignment feature is available in Placement Edit Application mode. It was introduced in the Allegro PCB Editor 16.3 release and now enhanced in 16.6 to support the following new options:

• Alignment Edge
  • When aligning vertically, select ‘left’ or ‘right’ as the edge to base the alignment on
  • When aligning horizontally, select ‘top’ or ‘bottom’ as the edge to base alignment on…

The SPB 16.6 Release is available! You can download it from the Cadence Software downloads site.

Here are just a few press announcements on the 16.6 release –

New Allegro 16.6 Release Accelerates Timing Closure on High-Speed PCB Interfaces by 30 to 50 Percent

Announcing OrCAD 16.6—A One-Two Punch for Mainstream PCB Engineers

Cadence Allegro Accelerates Product Creation Through Efficient Collaborative ECAD Environment…

The well attended Mixed-Signal Technology Summit last month really demonstrated the tremendous interest our customers have in learning new methodologies and techniques for mixed-signal designs. I would like to share some interesting data points based on a survey from the attendees of the event. Among the close to 200 attendees, 73% were designers with analog centric design experiences. However, about 24% of them declared…

Last week over 35 power users from over a dozen companies came together for the latest installment of "Club Formal" -- a user group meeting exclusively focused on topics in formal analysis and Assertion-Based Verification (ABV).  This instance of Club Formal featured several papers from Silicon Valley power users on expert-level techniques, as well as highlights of new "verification apps" that are highly automated…

The 16.5 Allegro PCB Editor now has the added ability to accentuate objects and layers in Allegro PCB Editor by providing pattern support.

Read on for more details …

Stipple pattern support is provided through the assign color, highlight and color commands. The assign color command allows you to assign custom stipple patterns to objects in addition to assigning the color and default highlight patterns it currently…

A press release and a blog post caught my attention this week (October 15, 2012), and they have clearly demonstrated Cadence's leadership in 20nm process nodes and mixed-signal solutions. The press release is titled "TSMC Selects Cadence Virtuoso and Encounter Platforms for its 20nm Design Infrastructure, Spanning Custom/Analog, Digital and Mixed-Signal Design." This press release emphasizes that TSMC's…

The 16.5 Allegro Design Workbench (ADW) now supports multiple shopping lists.

In a nutshell, multiple shopping lists support these capabilities:

•    Provide viewing multiple lists from:
–    One or more common list directories
–    One or more other project directories
–    One or more specific files
–    Lists created from an outside source in the proper format can be referenced

•    Functions for:
–…

The approach shown in this post (part 4) will only work in Virtuoso IC 6.1; it depends on features which are…

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e, SystemVerilog, SystemC, and C/C++ into one simulation is basic but insufficient for SoC verification.  The question asked by SoC verification…

[Preface: the upcoming "Club Formal" on October 17 here at the Cadence San Jose campus will also touch on this topic - please join us!]

While it's now common knowledge that there are many benefits to using simulation technology within a metric-driven verification (MDV) flow, as it turns out there are also an equal number of benefits to using formal analysis technology in such a flow as well.  Even better,…

Indexed ports are used to access composite HDL objects in SystemVerilog (SV). Their most frequent use is to access SV multi-dimensional arrays by defining a simple indexed port and accessing the array elements with the port indexes.

Ports in general, and Indexed ports specifically, are static objects that need to be known in the environment build up. Indexed ports were implemented in such a way that each port needs SV…

A recently published AppNote on converting a PADS ASCII file to Allegro PCB Editor has eased the life of many users by providing a step-by-step methodology and appropriate debugging techniques. It also covers various scenarios where Allegro PCB Editor generates errors or warnings during the translation, and explains how to debug errors and obtain a neat board file (.BRD) to be used in Allegro PCB Editor.

The PADS translator…

Prior to the 16.5 release, the search capabilities in Allegro Design Entry HDL (DEHDL) have been quite limited. This has changed in the 16.5 release with the introduction of a new toolbar for page level search and an Advanced Search and Navigate functionality.
 
Read on for more details …

The Page Search option enables you to search for text on the current page. The text can be a symbol text, net name, property or…

In the Allegro PCB SI 16.5 release, static IR drop analysis has been integrated into PDN (power delivery network) analysis, with several new features added, such as current density display and the display of current direction.

Read on for more details …

Analyze Menu

To invoke Static IR Drop analyze, select Analyze > Static IRDrop Analysis at the bottom of the PDN Analysis form:

 

This will open the following window…

I recently came across a Wall Street Journal article,"ARM Chases Bigger Slice of Smaller Chips,"  that provides a very interesting perspective on how ARM is positioned to capture the microcontroller market, which is its next growth area. ARM based microprocessors are clearly dominating the mobile products from smart phones to tablets across Windows, Android and IOS mobile eco-systems. Most of these devices are…