Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow.

The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

The countdown has begun to bid farewell to 2022. Many of us are juggling last-minute work errands and holiday preparations, but we know the much-deserved year-end break is around the corner. ‘Tis the time of the year we look forward to Dulce Domum or Home Sweet Home when we sit in our snug armchair and reminisce about the happy events and accomplishments of the year gone by. It's just the right mood to revisit the blog topics that celebrated Voltus innovations throughout the year. Here is a brief description of each of the 8 Voltus Voice posts we published, all in one place for you. Let’s dive in!

Hierarchical Power Integrity Analysis—Why xPGV Modeling Is the Designer's Best Choice for Mega-Sized Chips

Explore how Voltus Extreme Modeling (XM) plays a notable role in addressing the EM-IR analysis challenges on a full-chip design. This solution offers a significant speedup in the runtime over full flat analysis, process efficiency that mega-sized chips demand, and acceleration of the design cycle.

Early Power and Thermal Integrity Analysis in 3D-ICs - Why it Really Matters?

Early analysis is extremely critical in 3D-ICs since changing the die stack up later in the design process is extremely difficult or even impossible. In this blog post, we present an insightful webinar chaired by Voltus Product Marketing Director, Rajat Chaudhry, on how to perform power integrity and thermal integrity analysis in 3D-ICs from early planning to signoff.

Simplifying Power Signoff for HPC Systems: Super-Charge your Power Methodology with Event-Based Power Analysis

Ever wonder how to handle ultra-large designs with very long simulation vectors? Learn how this Voltus power analysis solution enables designers to run an accurate event-based power analysis on large vectors and designs without the need for reserving large servers.

Overcoming Design Challenges Using Voltus Documentation—The Definitive Training Video

We talk about the training video that gives a quick rundown on accessing Voltus Documentation via Cadence Help, Voltus Graphical User Interface (GUI), and Command Line Interface (CLI). Voltus Documentation plays a crucial role in enhancing user experience, empowering you to learn, explore, and troubleshoot issues in an easy and more autonomous manner.

Five Great Features to Enhance Your Full-Chip Power Signoff

In this post, we discuss five useful features to help you navigate through a variety of power integrity challenges. From Mixed Mode power (Vector-Based and Vectorless) analysis to Thermal Model generation to Scan Mode analysis, here are some cool strategies that will help you unlock the full potential of your design.

How to Find Functional Power Vectors that Matter Quickly

Smart windows profiling is a new and unique feature in Voltus where the tool can pick multiple windows of variable size to highlight the peak power or activity within the vector. The feature allows designers to specify the window type of their choice to be used for current construction and waveform file generation. The powerful vector profiling reports give good insight and debug solutions for the various design scenarios.

Voltus-Sigrity Collaboration Fuels System Innovation

Voltus is tightly integrated with six different Cadence tools at the different stages (digital, signoff, custom, verification, and IC package) of a design life cycle, providing a complete design and implementation solution. This post introduces the 'Chip-2-System Power Signoff' video series for a deeper insight into the goals and advantages of these integrations. Our post discusses the first video in the series—on Voltus-Sigrity X integration—a solution that enables designers to analyze system-level EMIR, resulting in seamless co-design and co-analysis of three domains—chip, package, and board.

How to Step Up Your Game with Target Power Vectorless Dynamic EMIR Analysis

Our last blog post of the year described how power target methodology with user-defined power comprehensively supports early identification of grid weaknesses from the region or block-based peak power demands without using vectors. Vectorless power analysis enables designers to perform different scenario-based dynamic-voltage-drop (DVD) analyses and achieve better results. The new power solution can be leveraged to meet the design challenges in terms of scalability, design coverage, and runtime.

Hope these features and strategies shared via 2022's blog posts enable you to steer through the design challenges of 2023 with confidence.
Happy holidays!

Related Resources

Product Manuals	Voltus IC Power Integrity Solution User Guide
Blogs	Voltus and Azure—no power integrity challenge too big to solve
Video	Chip-2-System Power Signoff – Part 1: Voltus-Sigrity X Integration CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis What's New in Voltus IC Power Integrity Solution - SSV 22.1

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

Subscribe to receive email notifications about our latest Digital Design blog posts.