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Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi
• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman
• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML
Digital Design
Latest blogs

Training Insights – Why Is RTL Translated into Gate-Level Netlist?

Have you ever wondered how those tiny chips in your phone or computer actually work…

• 3 min read
Physical verification , conformal , Static timing analysis , DFT , EDI , Modus DFT , Tempus , Gate level simualtion , LEC , Signoff Analysis , DRC , STA , RTL-to-GDSII digital implementation digital design design verification Xcelium Verisium Genus Modus DFT Conformal Innovus Tempus Voltus Quantus , Floorplanning , RTL-to-GDSII , verisium , Xcelium Logic Simulator , Logic Design , Digital Implementation , Innovus , Timing analysis , Power Analysis , Synthesis , Placement , Quantus , Tempus Timing Signoff Solution , physical implementation , vManager , Modus ATPG , verification

Voltus Voice: Breaking Ground with Voltus-InsightAI—A Detailed Exploration

In the 2nd blog on Voltus InsightAI, we examine the intricate technologies that make…

• 5 min read
artificial intelligence , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , Innovus Implementation System , Generative AI , Power Integrity , Voltus InsightAI , Placement , EMIR

Forget the Wireloads! Gear Up for Physical Synthesis to Tackle PPA Results!

The traditional synthesis process relies on the Wireload models to estimate the delays…

• 3 min read
digital badge , Genus , training bytes , physical design , Synthesis , online training , Online Support

Training Insight – Make Your Design Testable with Cadence Test Solution

Testing digital IC designs is crucial for several reasons, including cost savings…

• 2 min read
DFT , Genus Synthesis Solution , Synthesis , Modus ATPG

New to Equivalence Checking? Restart from the Basic Concepts

New Training Bytes Available: "What Is Mapping?" and “What Is Comparison?” Equivalence…

FormerMember • 3 min read
digital badge , conformal , Cadence Online Support , training , training bytes , digital implementation

Let's Replay the Process of Power Estimation with the Power of 'x'!

Power analysis is one of the important aspects of the IC design flow. In today's…

• 3 min read
annotation , debug , Joules , training , training bytes , power estimation , Power Analysis , Genus Synthesis Solution , RTL design , power , activity , Joules RTL Design Studio

Binge on Chip Design Concepts this Weekend!

In today's semiconductor era, every minute, you always look for the opportunity to…

• 2 min read
Genus , training , YouTube , training bytes , Digital Implementation , Synthesis

Voltus Voice: Breaking Ground with Voltus InsightAI—AI’s Debut in EM-IR Analysis

This blog introduces Voltus InsightAI, an AI-driven in-design solution for early…

• 4 min read
artificial intelligence , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , Generative AI , Power Integrity , Voltus InsightAI , Innovus , EMIR

Cadence Learning and Support: Installation and Licensing Help via Chatbot

In recent years, the requirements and performance goals for designers have become…

• 2 min read
COS , chatbot , Cadence Online Support , training bytes , Digital Implementation , cadence learning and support

Cadence Learning and Support: New Courses Section in Content Notification Email

As you may already know, you can get notified via Cadence Learning and Support website…

• 2 min read
Cadence Online Support , training , Digital Implementation , online training , cadence learning and support

Learn Fast and Make Things

“Move fast and break things,” a motto coined by Mark Zuckerberg, captures the ethos…

• 2 min read
digital badge , place and route , Digital Implementation , Innovus , online training

Unveiling the Blueprint for Next-Gen SoC with Cadence Tools

Insights From a Conversation With Matti Käyrä of SoC Hub, Finland The relentless…

• 4 min read

Revolutionizing Circuit Design with Quantus DSPF Interactive Output

In the field of electronics design, validating circuit designs has always been a…

• 4 min read
debug , DSPF , Quantus , signoff closure , debugging

Training Insights – Dive into ATPG Flow with Cadence Modus DFT Software Solution

The prominent components of the EDA flow, like synthesis, place and route, and signoff…

• 2 min read
DFT , Modus DFT , ATPG

It’s the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!

In this fast-changing world, every minute, you grab the opportunity to enhance your…

• 1 min read
digital badge , DSG , Genus , Joules , training , training bytes , online training

Training Insights – Struggling with Synthesis to Achieve Best PPA Results?

The ultimate goal of the Cadence Genus Synthesis Solution is very simple: deliver…

• 2 min read
digital badge , Genus , online courses , exam , training , training bytes , Genus Synthesis Solution , Synthesis , online training , Online Support

Training Bytes: They May Be Shorter, But the Impact Is Stronger!

Training Byes are short technical videos, but they are designed to help you in multiple…

• 3 min read
ECO , Conformal ECO Designer , conformal , DFT , DSG , Low Power , videos , online courses , LEC , DRC , LVS , 3Dblox , 3DIC , Setup and Hold Analysis , Digital Design Flow Videos , training bytes , ecoDesign , Encounter Digital Implementation , Innovus , Power Analysis , Genus Synthesis Solution , signoff , Tempus Timing Signoff Solution , Modus ATPG , LMS , cadence learning and support

The Cloud Advantage: Optimizing PPA and Delivery with Cadence Cerebrus

Graphics processing units (GPUs) have significantly transcended their original purpose…

• 4 min read
On Cloud , PPA Improvement , Cadence Cerebrus , Delivery

Digital Design - New Training Releases, Blogs, Videos and Digital Badges in 2023

Another year has gone by, and – as always - we will not miss to look back at our…

• 3 min read
blended training , artificial intelligence , Low Power , Genus , Tempus , Integrity 3D-IC Platform , modus , midas , cerebrus , Cadence Online Support , hierarchical design , RTL-to-GDSII , Joules , training , webinar , Voltus , training bytes , Digital Implementation , Innovus , digital full flow , online training

Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!

If you missed joining or registering for the RTL-to-GDSII webinar, the complete recording…

• 2 min read
DFT , Genus , Designing a Complete Chip Using the RTL-to-GDSII Flow Recording , Designing a Complete Chip Using the RTL-to-GDSII Flow , LEC , webinars , Floorplanning , RTL-to-GDSII , Xcelium Logic Simulator , Logic Design , Digital Implementation , Innovus , Synthesis , Placement , Tempus Timing Signoff Solution , physical implementation , vManager , Modus ATPG

The Best Way to Learn - Innovus Implementation with Stylus Common UI

The Cadence Innovus Implementation System provides an integrated solution for RTL…

• 2 min read
digital badge , live training , Stylus Common UI , Innovus Implementation System , Cadence training , Digital Implementation , cadence learning and support

The Best Way to Learn – Voltus Power-Grid Analysis with Stylus Common UI

Power integrity is becoming one of the most pressing challenges at advanced nodes…

• 3 min read
digital badge , ECO , live training , Voltus IC Power Integrity Solution , Power and Rail analysis , Cadence training , Digital Implementation , EMIR , cadence learning and support

Let's Discover the Secret to Enhance Design's PPAC in a Single Cockpit!

Traditionally, you would do power, performance, area, and congestion (PPAC) analysis…

• 3 min read
performance , debug , training , congestion , PPAC , training bytes , area , power , Joules RTL Design Studio

Voltus Voice: Navigating 2023 - A Recap of our Blogging Odyssey

A recap of the power integrity posts in the Voltus Voice blog series through 2023…

• 6 min read
Early Rail Analysis , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , 3D-IC , RTL-to-GDSII , Thermal Analysis , Power Analysis , vector profiling , Multi-Chiplet Design

Voltus Voice: Multi-Chiplet Marvels – Exploring Chip-Centric Thermal Analysis

Dive into the intricate world of chip-centric thermal analysis to understand its…

• 4 min read
Celsius Thermal Solver , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , Integrity 3D-IC Platform , EM-IR , Thermal Analysis , 3D-IC Technology , system planning , Multi-Chiplet Design

Cadence Doc Assistant: Elevate Your Knowledge With Our Next-Gen Help System

The SSV 23.1 release comes with a brand-new content delivery application called Cadence…

• 3 min read
documentation , Silicon Signoff and Verification , Search , SSV , Cadence Doc Assistant , help , Cadence Help , 23.1

SSV 23.1 Base Release Now Available

The Silicon Signoff and Verification (SSV) 23.1 release is now available for download

• 4 min read
Celsius Thermal Solver , Silicon Signoff and Verification , Die-Model Grid Reduction , Voltus IC Power Integrity Solution , Silicon Prediction , hyperscale , SSV23.10 , Thermal Analysis , Power Analysis , Tempus Timing Signoff Solution , Skew Robustness , Doc Assistant

Training Insights – Implement Your Digital Circuits Using Virtuoso Digital Implementation…

Are you excited to know more about the Virtuoso Digital Implementation flow, which…

• 3 min read
Innovus Implementation System , Virtuoso Digital Implementation , training bytes , Digital Implementation , Genus Synthesis Solution , Mixed Signal Designers , Analog on top designs
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