Voltus IC Power Integrity Solution is a power integrity and analysis signoff solution integrated with the full suite of Cadence design implementation and signoff tools to deliver the industry’s fastest design closure flow. This blog series aims to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

As we approach the final stretch of our 2023 blogging journey, let us look back at the milestones that guided us through the digital landscapes and helped in overcoming the roadblocks of power integrity and analysis signoff. In this journey, every post has been a pit stop – a chance to refuel our minds and recalibrate our perspectives. Just as a well-planned route considers various destinations and exciting experiences, our blogs have covered a terrain that spans different innovative solutions and new tech-insights to meet the challenges in our digital designs.
So, before we steer our way towards 2024, let us marvel at the diverse destinations we visited in 2023.

Voltus-Innovus Integration Avoids Potential Power-Signoff Issues

Want a more robust power grid in the early design stage? Wondering how to design and optimize a power grid without actual floorplanning and routing? Voltus integration with Innovus can help you achieve that. Our blog post talks about the second installment in the "Chip-2-System Power Signoff" video series where we introduce an Integrated Signoff Closure Flow involving a tight integration between Voltus and Innovus.

How Voltus RTL Power Analysis Enables Sustainable Innovation

Sustainability is the need of the hour and power efficiency is a critical area in chip design that has a cascading effect on energy conservation across systems. In this blog post, we show how the RTL-based power analysis can help achieve better power, performance, and area (PPA), reduce power consumption, and enable sustainable innovation for our next-generation technologies.

Voltus-Celsius Integration for System Analysis

We talk about the third video in the "Chip-2-System Power Signoff" video series in which Voltus integrates with Celsius to achieve faster system-level thermal and power integrity analysis and closure. This integration allows the engineering teams to combine electrical and thermal analysis, simulating the flow of both electricity and heat for an accurate system-level thermal simulation.

3 Commands You Should Know to Debug Power Using Voltus

In this post, we discuss three useful commands to debug power issues early in the design process, thereby minimizing power consumption. By using these commands to retrieve power-related data, you can ensure that the design meets its power requirements in shorter development cycles.

Multi-Chiplet Marvels - Harnessing Power by Early Analysis of 3D-IC Designs

Learn how the Voltus 3D-IC ERA can help overcome the challenges of 3D-IC early power integrity analysis. Through the Voltus 3D-IC ERA flow, you can complete system planning, PG specification, and rail analysis in one go, eliminating the need to handle the scripts and commands in multiple-point tools. By getting early feedback from the 3D-IC ERA flow, you can get the benefits of a robust power delivery structure and avoid over-design of individual chiplets.

 Multi-Chiplet Marvels - Stepping into the 3D-IC Signoff Realm

3D-IC technology holds great potential in areas like artificial intelligence (AI) or machine learning (ML), high-performance computing like weather modelling and aerospace technology. At the same time, it is important to acknowledge that the increased design density in 3D-ICs also brings forth challenges such as thermal issues, crosstalk, and power and IR violations. In this blog post, we discussed how the Voltus 3D-IC signoff solution can help combat these issues and prevent costly and time-consuming re-spins.

 Elevate Your Power Signoff Approach Using 3D Vector Profiling

In this post, we talked about 3D Vector Profiling, a tile dimension approach for power density calculation during power signoff. The 3D vector profiling flow ensures that all critical areas and scenarios are methodically covered. It lets you discover the IR drop hotspots in the design and make informed decisions about power management and optimization, reducing the risk of late-stage design revisions.

Multi-Chiplet Marvels – Exploring Chip-Centric Thermal Analysis

The last pit-stop of our 2023 blogging journey was at Chip-centric thermal analysis, where we explored the significance of thermal analysis in 3D-IC designs. It serves as a linchpin in ensuring both the performance and durability of products. By anticipating the severity of thermal issues in the upcoming technology nodes, the chip-centric thermal analysis is a giant leap towards on-die and full-system PPA-driven solution.

We hope these 2023 blogging destinations helped you explore the new features and solutions for your design problems. Cheers to the journey and new learning that await us in the coming year.

Related Resources

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.