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Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
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What Is Viral in CXL 3.0?

Introduction to CXL 3.0 CXL 3.0 is an open-standard interconnect technology that…

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CXL , Verification IP , viral , Functional Verification

Understanding Embedded USB2 (eUSB2) and its usage

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VIP , USB , eUSB2

Unraveling PCIe 6.0 Loopback and Digital Near-End Loopback Feature

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PHY , NELB , Loopback , Gen6 , PCIe 6.0

DisplayPort 2.1 vs DisplayPort 1.4: A Detailed Comparison of Key Features

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Verification IP , Functional Verification , DisplayPort

Building Verification Infrastructure for Complex PCIe Verification

Introduction PCIe (Peripheral Component Interconnect Express) is a high-speed serial…

• 4 min read
Verification IP , Functional Verification , PCIe , pcie gen6

Navigating Cache Coherence: The Back-Invalidate Feature in CXL 3.0

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CXL , performance , Verification IP , Functional Verification , coherent , HIgh Speed Interconnect

Automate Regression Failure Triage with the Cadence Verisium

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Versium , Auto Triage , Regression

Revolutionize System Verification Flow with a Holistic Approach

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wholistic approach , system level , System Level Design Verification , verification

Ethernet Encryption: Harnessing the Power of IPSec Shields

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Leveraging AI to Optimize the Debug Productivity and Verification Throughput

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Insights Into the Evolutions and Optimizations of PCIe 6.0

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Verification IP , VIP , PCIe , Optimize , pcie gen6 , PCIe 6.0

Maximise Verification Reuse with Cadence Perspec System Verifier

Are You Tired of Countless Hours Manually Creating Complex System-Level Coverage…

• 4 min read
verification reuse , perspec system verifier , Coverage Level Ststem Driven tests , system-level verification , SoC level test suit

USB4 Version 2.0 – Link Configurations

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• 2 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2 , usb4 router

Accelerate Your Debug with Verisium - Cadence's Next-Generation Debug Solution

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• 3 min read
Low Power , Functional Verification , Verisium Debug , VerisiumDebug

Be Optimistic About Xcelium's New X-Pessimism App!

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Functional Verification , x-pessimism , xcelium , simulation

Verifying Compliance During PCIe Re-Timer Testing Poses Challenges

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Re-timer , System Design and Verification , VIP , PCIExpress , compliance , Polling Compliance

USB4 Version 2.0 – Gen4 High-Speed Lane Initialization and Training

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USB4 VIP , USB4v2 , usb4 , USB4 Version 2 , usb4 router

Why Do You Need a Simulator-Friendly Debug Tool for UVM Debug?

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• 6 min read
uvm , debug , Testbench simulation , testbench , VerisiumDebug

Enhancing Network Security with MacSec: Protecting Ethernet Communications

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security , Automotive , Ethernet 800G , Verification IP , Ethernet VIP , Functional Verification , System Design and Verification , VIP , Ethernet standards , Automotive Ethernet , encryption , Ethernet , MacSec , Ethernet 400G , verification

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Verification IP , encryption , PCIe , pcie gen6 , IDE

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Verification IP , VIP , PCIe , feature , PCIe 6.0

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Low Power , Verisium Debug , xcelium , verification

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cadence , Xcelium Logic Simulator , xcelium simulator , verification

Best Practices to Achieve the Highest Performance Using Xcelium Logic Simulator …

Xcelium Logic Simulator Profile Analysis Our previous post discussed measuring parameters…

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Xcelium Logic Simulator , profile analysis , xcelium simulator , xcelium , best practices , verification

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• 3 min read
SystemVerilog , Verification IP , PCIe , pcie gen6 , PCIe 6.0 , System Design and Verification , verification

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