• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    Get selected nets from Navigator in IC61 Locked

    14309 views
    2 replies
    Latest over 16 years ago
    by Yaosan
  • Discussion

    Assura RCX fails Locked

    20995 views
    12 replies
    Latest over 16 years ago
    by pitter
  • Discussion

    Netlist mismatch between schematic & .brd file Locked

    1965 views
    4 replies
    Latest over 16 years ago
    by Khurram
  • Discussion

    Simulation data storage directory Locked

    14632 views
    2 replies
    Latest over 16 years ago
    by tkhan
  • Discussion

    Adding a pad to a footprint? - in Allegro Locked

    3618 views
    4 replies
    Latest over 16 years ago
    by JGeens
  • Discussion

    Working with Scratch Cellview Locked

    16429 views
    3 replies
    Latest over 16 years ago
    by annegry12
  • Discussion

    aligning dxf import with grid Locked

    15887 views
    7 replies
    Latest over 16 years ago
    by Khurram
  • Discussion

    import OpenAccess to Cadence Virtuoso and do LVS check Locked

    15641 views
    3 replies
    Latest over 16 years ago
    by Quek
  • Discussion

    error occured while importing netlist Locked

    14770 views
    4 replies
    Latest over 16 years ago
    by ryangarg05
  • Discussion

    wavescan (ic5141) Locked

    13824 views
    1 reply
    Latest over 16 years ago
    by Quek
  • Discussion

    Harmonic Parametric Locked

    15116 views
    5 replies
    Latest over 16 years ago
    by AMSboston
  • Discussion

    Layout XL SKILL functions extremely slow in L environment Locked

    16847 views
    6 replies
    Latest over 16 years ago
    by Andrew Beckett
  • Discussion

    Does setPlanDesignMode work with multiPlanDesign ??? Locked

    13421 views
    1 reply
    Latest over 16 years ago
    by BobD
  • Discussion

    Mixed simulations + vhdl Locked

    13861 views
    2 replies
    Latest over 16 years ago
    by acomerma
  • Discussion

    how to prevent the use of specific library cells for some instance in the design? Locked

    15155 views
    4 replies
    Latest over 16 years ago
    by dacyace24
<>

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information