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  • Discussion

    QRC substrate_connection -device_list option Locked

    1063 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    final original layout for Parasitic Aware Design Flow RAK Locked

    8725 views
    2 replies
    Latest over 3 years ago
    by delgsy
  • Discussion

    Can we do synthesis by using variables in generate block Locked

    10242 views
    0 replies
    Started over 3 years ago
    by RFStuff
  • Discussion

    How to make a default for Plugins Simulation as other Locked

    9811 views
    5 replies
    Latest over 3 years ago
    by TonyTang
  • Discussion

    Results Display Window Locked

    13142 views
    3 replies
    Latest over 3 years ago
    by henker
  • Discussion

    How To achieve pulse supply voltage with four different levels of voltage Locked

    19072 views
    6 replies
    Latest over 3 years ago
    by Omar Ghazal
  • Discussion

    Gradual Aging Simulations not passing variables correctly Locked

    8987 views
    0 replies
    Started over 3 years ago
    by gmadrid
  • Discussion

    Rename all labels of an instance in a schematic Locked

    10548 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    set_db cts_clustering_source_group_max_cloned_fraction 0.2 Locked

    11960 views
    3 replies
    Latest over 3 years ago
    by william406
  • Discussion

    Reading data from a file and assign those into a parametric array in verilogAMS Locked

    13439 views
    4 replies
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    Open Layout Instance in New Tab doesn't work in Ic 6.1.8.500.13 Locked

    2049 views
    3 replies
    Latest over 3 years ago
    by Laurentz
  • Discussion

    CPH ID and soft block ID Locked

    9400 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    Cadence Schematic - customizing DC Operating Points annotation permanently Locked

    4568 views
    4 replies
    Latest over 3 years ago
    by firebolt
  • Not Answered

    Allegro 17.4 EDA File Export 0

    9150 views
    1 reply
    Latest over 3 years ago
    by DavidJHutchins
  • Discussion

    Maestro config sweep causing changes netlisting for bus "<" Locked

    4220 views
    5 replies
    Latest over 3 years ago
    by brianbranch
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