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  • Discussion

    Remote-Host Simulation in ADE-L (or ADE Assembler) Does Not End Locked

    10896 views
    1 reply
    Latest over 3 years ago
    by DrSeo
  • Suggested Answer

    Listing DRA names in file directory 0

    9960 views
    2 replies
    Latest over 3 years ago
    by vimaldevlpr
  • Discussion

    Convert a bunch of analog waveform into integer value Locked

    11429 views
    1 reply
    Latest over 3 years ago
    by delgsy
  • Discussion

    How to run simulations in Explorer/Assembler starting from a netlist? Locked

    5954 views
    8 replies
    Latest over 3 years ago
    by FormerMember
  • Discussion

    Inherited connections and VXL.....again. Locked

    12386 views
    4 replies
    Latest over 3 years ago
    by kenc184
  • Discussion

    How do I set valid layers on bootup of Cadence Virtuoso XL? Locked

    11140 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Not Answered

    Allegro – Tip of the week: Is my database optimized for performance? 0

    9085 views
    0 replies
    Started over 3 years ago
    by PCBTech
  • Discussion

    How to include a verilog file/functional view in HED? Locked

    7639 views
    8 replies
    Latest over 3 years ago
    by Frank Wiedmann
  • Discussion

    Can someone please help with the syntax for a Navigator specific bindkey Locked

    9486 views
    1 reply
    Latest over 3 years ago
    by AurelBuche
  • Discussion

    Automatically loading some libraries into my cds.lib Locked

    12475 views
    1 reply
    Latest over 3 years ago
    by AurelBuche
  • Answered

    Full round shape and route keepout problem 0

    11049 views
    2 replies
    Latest over 3 years ago
    by soll
  • Not Answered

    Align pins of components 0

    12774 views
    5 replies
    Latest over 3 years ago
    by LSAUGE
  • Discussion

    How to find floating metals/vias using skill code Locked

    5155 views
    2 replies
    Latest over 3 years ago
    by prasadtammana
  • Suggested Answer

    Interlayer spacing constraint DRC (detect soldermask layer & silkscreen layer conflict) 0

    3719 views
    3 replies
    Latest over 3 years ago
    by ichliebedich
  • Discussion

    Skill code to generate pins and label on metal by a bindkey Locked

    13178 views
    3 replies
    Latest over 3 years ago
    by Andrew Beckett
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