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  • Discussion

    probe tcl syntax to save variables inside automatic tasks in systemverilog Locked

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    Latest over 4 years ago
    by StephenH
  • Discussion

    INNOVUS Placement regular structures Locked

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    1 reply
    Latest over 4 years ago
    by Dimo M
  • Not Answered

    OrCAD Capture - Version 17.4-2019-S016-Issue Export - PDF 0

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    4 replies
    Latest over 4 years ago
    by RFinley
  • Discussion

    annotate text to a schematic from a file every time the schematic is opened or refreshed Locked

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    2 replies
    Latest over 4 years ago
    by DerekH
  • Discussion

    Changing the parameter inside model file for creating multiple corner cases. Locked

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    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    CIW not showing variable data when load the code in SKILL IDE Locked

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    4 replies
    Latest over 4 years ago
    by Keans
  • Discussion

    Using SystemC models in ADE Locked

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    Latest over 4 years ago
    by ChrisEAS
  • Discussion

    how to parse string and number Locked

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  • Discussion

    How to simulate a mixed-signal system if power-supply is time-varient Locked

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    0 replies
    Started over 4 years ago
    by SpiceMonkey
  • Discussion

    creating ADE-L state file from Skill script simulation Locked

    11150 views
    2 replies
    Latest over 4 years ago
    by HansB
  • Discussion

    I want to get better at PCB design. But I don't know where to start... Locked

    906 views
    0 replies
    Started over 4 years ago
    by kmiller10
  • Discussion

    Making skill form and logic for IDX transfer.

    9935 views
    5 replies
    Latest over 4 years ago
    by RFinley
  • Discussion

    Square pins on symbols in verilogin Locked

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    2 replies
    Latest over 4 years ago
    by CSCNalu
  • Discussion

    Create negative artwork or pdf?

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    2 replies
    Latest over 4 years ago
    by cemmanuel
  • Discussion

    Why does Stratus HLS report this error? Locked

    19274 views
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    Latest over 4 years ago
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