Custom IC Design

Latest Posts

Discussion

failed to simulate veriloga in hspice : call to epvaHDLcgen failed

Category: Custom IC Design

By zongya

$usertype
•
updated over 10 years ago by zongya

2 replies • 16716 views
Discussion

descend to new window

Category: Custom IC Design

By Karev11

$usertype
•
updated over 10 years ago by Andrew Beckett

4 replies • 16473 views
Discussion

How to get a faster transient analysis?

Category: Custom IC Design

By Pyroblast

$usertype
•
updated over 10 years ago by FormerMember

1 replies • 15479 views
Discussion

Connections between Bulk or gate and source for a PMOS

Category: Custom IC Design

By Leof

$usertype
•
updated over 10 years ago by Leof

10 replies • 27946 views
Discussion

Spectre nport BBSPICE interpolation/ BBSPICE standalone

Category: Custom IC Design

By RobinCommander

$usertype
•
updated over 10 years ago by Andrew Beckett

1 replies • 15670 views
Discussion

Virtuoso Chip Assembly Router

Category: Custom IC Design

By b53649

$usertype
•
updated over 10 years ago by ColinSutlieff

1 replies • 14231 views
Discussion

Setting option duplicatemodel=ignore in spectre does not work

Category: Custom IC Design

By Frode Telsto

$usertype
•
updated over 10 years ago by Frode Telsto

7 replies • 6325 views
Discussion

Transient Noise Analysis

Category: Custom IC Design

By uzzymoh

$usertype
•
updated over 10 years ago by Frank Wiedmann

1 replies • 14467 views
Discussion

Howto run parametric simulations using Matlab & Spectre

Category: Custom IC Design

By marten

$usertype
•
updated over 10 years ago by Andrew Beckett

3 replies • 2328 views
Discussion

Technology hierarchy error that causes objects can't be selected.

Category: Custom IC Design

By LoTJF

$usertype
•
updated over 10 years ago by LoTJF

8 replies • 5433 views
Discussion

Virtuoso IC6.16 - DC simulation - Annotate DC OP failed

Category: Custom IC Design

By Chrisss

$usertype
•
updated over 10 years ago by Andrew Beckett

1 replies • 805 views
Discussion

How to plot Id-Vg at different channel length by cadence spectre ?

Category: Custom IC Design

By richardyuan

$usertype
•
updated over 10 years ago by Andrew Beckett

7 replies • 17975 views
Discussion

Unable to generate Proper Layouts

Category: Custom IC Design

By SHEKHARvnit

$usertype
•
updated over 10 years ago by Andrew Beckett

6 replies • 15033 views
Discussion

One testbench for different analysis (dc, trans,...)

Category: Custom IC Design

By marten

$usertype
•
updated over 10 years ago by marten

2 replies • 15576 views
Discussion

How can I automate noise margin calculation ?

Category: Custom IC Design

By marten

$usertype
•
updated over 10 years ago by marten

11 replies • 24542 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.